Home
last modified time | relevance | path

Searched +full:0 +full:x53000 (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.15/arch/powerpc/boot/dts/
Dpq2fads.dts26 #size-cells = <0>;
28 cpu@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x60>;
52 ranges = <0x0 0x0 0xff800000 0x800000
53 0x1 0x0 0xf4500000 0x8000
54 0x8 0x0 0xf8200000 0x8000>;
[all …]
Dmpc8272ads.dts25 #size-cells = <0>;
27 PowerPC,8272@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x40>;
52 ranges = <0x0 0x0 0xff800000 0x00800000
53 0x1 0x0 0xf4500000 0x8000
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dexynos54xx.dtsi42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
78 reg = <0x101c0000 0xb00>;
95 reg = <0x101d0000 0x100>;
101 reg = <0x12d10000 0x100>;
110 reg = <0x12ca0000 0x1000>;
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/sram/
Dsram.yaml152 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
156 ranges = <0 0x5c000000 0x40000>;
159 reg = <0x100 0x50>;
163 reg = <0x1000 0x1000>;
168 reg = <0x20000 0x20000>;
183 reg = <0x02020000 0x54000>;
186 ranges = <0 0x02020000 0x54000>;
188 smp-sram@0 {
190 reg = <0x0 0x1000>;
195 reg = <0x53000 0x1000>;
[all …]
/Linux-v5.15/drivers/virt/vboxguest/
Dvmmdev.h17 #define VMMDEV_PORT_OFF_REQUEST 0
50 #define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED BIT(0)
72 #define VMMDEV_EVENT_VALID_EVENT_MASK 0x000007ffU
79 #define VMMDEV_VERSION 0x00010004
81 #define VMMDEV_VERSION_MINOR (VMMDEV_VERSION & 0xffff)
87 #define VMMDEV_REQUEST_HEADER_VERSION 0x10001
124 #define VMMDEV_MOUSE_GUEST_CAN_ABSOLUTE BIT(0)
155 #define VMMDEV_MOUSE_RANGE_MIN 0
157 #define VMMDEV_MOUSE_RANGE_MAX 0xFFFF
181 #define VMMDEV_HVF_HGCM_PHYS_PAGE_LIST BIT(0)
[all …]
/Linux-v5.15/drivers/infiniband/hw/qib/
Dqib_7220_regs.h37 #define QIB_7220_Revision_OFFS 0x0
38 #define QIB_7220_Revision_R_Simulator_LSB 0x3F
39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7220_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
42 #define QIB_7220_Revision_R_Emulation_Revcode_LSB 0x28
43 #define QIB_7220_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF
44 #define QIB_7220_Revision_BoardID_LSB 0x20
45 #define QIB_7220_Revision_BoardID_RMASK 0xFF
46 #define QIB_7220_Revision_R_SW_LSB 0x18
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/umc/
Dumc_6_7_0_offset.h29 // base address: 0x50f00
30 …MCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
31 …e regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
32 …MCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
33 …e regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
37 // base address: 0x50000
38 …UMCCH0_0_BaseAddrCS0 0x0000
39 …e regUMCCH0_0_BaseAddrCS0_BASE_IDX 0
40 …UMCCH0_0_AddrMaskCS01 0x0008
41 …e regUMCCH0_0_AddrMaskCS01_BASE_IDX 0
[all …]
/Linux-v5.15/drivers/clk/qcom/
Dgcc-msm8916.c46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
[all …]
Dgcc-msm8939.c54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
Dgcc-msm8953.c41 .offset = 0x21000,
44 .enable_reg = 0x45000,
45 .enable_mask = BIT(0),
71 .offset = 0x21000,
84 .offset = 0x4a000,
87 .enable_reg = 0x45000,
101 .offset = 0x4a000,
114 { 1000000000, 2000000000, 0 },
119 .config_ctl_val = 0x4001055b,
120 .early_output_mask = 0,
[all …]