Searched +full:0 +full:x4aa40000 (Results 1 – 3 of 3) sorted by relevance
43 0 - split channel49 if cell 1 is 0 (split channel):52 for source thread IDs (rx): 0 - 0x7fff53 for destination thread IDs (tx): 0x8000 - 0xffff94 maximum: 0x3f105 maximum: 0x3f116 maximum: 0x3f150 reg = <0x0 0x485c0100 0x0 0x100>,151 <0x0 0x4c000000 0x0 0x20000>,152 <0x0 0x4a820000 0x0 0x20000>,[all …]
11 reg = <0x00 0x70000000 0x00 0x10000>;14 ranges = <0x0 0x00 0x70000000 0x10000>;24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */27 <0x01 0x00000000 0x00 0x2000>, /* GICC */28 <0x01 0x00010000 0x00 0x1000>, /* GICH */29 <0x01 0x00020000 0x00 0x2000>; /* GICV */38 reg = <0x00 0x01820000 0x00 0x10000>;39 socionext,synquacer-pre-its = <0x1000000 0x400000>;[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x00 0x70000000 0x00 0x200000>;25 ranges = <0x0 0x00 0x70000000 0x200000>;28 reg = <0x1c0000 0x20000>;32 reg = <0x1e0000 0x1c000>;36 reg = <0x1fc000 0x4000>;42 reg = <0x0 0x43000000 0x0 0x20000>;45 ranges = <0x0 0x0 0x43000000 0x20000>;50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */[all …]
