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/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dpq3-duart-0.dtsi2 * PQ3 DUART device tree stub [ controller @ offset 0x4000 ]
36 cell-index = <0>;
39 reg = <0x4500 0x100>;
40 clock-frequency = <0>;
41 interrupts = <42 2 0 0>;
48 reg = <0x4600 0x100>;
49 clock-frequency = <0>;
50 interrupts = <42 2 0 0>;
Dmpc8540ads.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8541cds.dts29 #size-cells = <0>;
31 PowerPC,8541@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc8555cds.dts29 #size-cells = <0>;
31 PowerPC,8555@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
47 reg = <0x0 0x8000000>; // 128M at 0x0
55 ranges = <0x0 0xe0000000 0x100000>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/spi/
Domap-spi.yaml109 reg = <0x2100000 0x400>;
114 #size-cells = <0>;
115 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
/Linux-v5.15/drivers/dma/ti/
Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
Dk3-psil-am64.c66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
71 PSIL_ETHERNET(0x4100, 21, 48, 16),
72 PSIL_ETHERNET(0x4101, 22, 64, 16),
73 PSIL_ETHERNET(0x4102, 23, 80, 16),
74 PSIL_ETHERNET(0x4103, 24, 96, 16),
76 PSIL_ETHERNET(0x4200, 25, 112, 16),
77 PSIL_ETHERNET(0x4201, 26, 128, 16),
[all …]
Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dstorcenter.dts30 #size-cells = <0>;
32 PowerPC,8241@0 {
34 reg = <0>;
37 bus-frequency = <0>; /* from bootwrapper */
47 reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
55 store-gathering = <0>; /* 0 == off, !0 == on */
56 ranges = <0x0 0xfc000000 0x100000>;
57 reg = <0xfc000000 0x100000>; /* EUMB */
58 bus-frequency = <0>; /* fixed by loader */
62 #size-cells = <0>;
[all …]
Dmpc8349emitxgp.dts25 #size-cells = <0>;
27 PowerPC,8349@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x10000000>;
50 ranges = <0x0 0xe0000000 0x00100000>;
51 reg = <0xe0000000 0x00000200>;
52 bus-frequency = <0>; // from bootloader
[all …]
Dmpc8308rdb.dts26 #size-cells = <0>;
28 PowerPC,8308@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
Dmpc8308_p1m.dts25 #size-cells = <0>;
27 PowerPC,8308@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x08000000>; // 128MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
53 ranges = <0x0 0x0 0xfc000000 0x04000000
[all …]
Dasp834x-redboot.dts25 #size-cells = <0>;
27 PowerPC,8347@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x8000000>; // 128MB at 0
51 reg = <0xff005000 0x1000>;
52 interrupts = <77 0x8>;
56 0 0 0xf0000000 0x02000000
[all …]
Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
Dtqm8540.dts27 #size-cells = <0>;
29 PowerPC,8540@0 {
31 reg = <0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
[all …]
Dtqm8541.dts26 #size-cells = <0>;
28 PowerPC,8541@0 {
30 reg = <0>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>;
51 ranges = <0x0 0xe0000000 0x100000>;
52 bus-frequency = <0>;
55 ecm-law@0 {
[all …]
Dtqm8555.dts26 #size-cells = <0>;
28 PowerPC,8555@0 {
30 reg = <0>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>;
51 ranges = <0x0 0xe0000000 0x100000>;
52 bus-frequency = <0>;
55 ecm-law@0 {
[all …]
Dstxssa8555.dts28 #size-cells = <0>;
30 PowerPC,8555@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>; // 33 MHz, from uboot
38 bus-frequency = <0>; // 166 MHz
39 clock-frequency = <0>; // 825 MHz, from uboot
46 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dmpc832x_rdb.dts26 #size-cells = <0>;
28 PowerPC,8323@0 {
30 reg = <0x0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x04000000>;
51 ranges = <0x0 0xe0000000 0x00100000>;
[all …]
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dgk104.c38 for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { in gk104_clkgate_enable()
42 nvkm_mask(dev, 0x20200 + order[i].offset, 0xff00, 0x4500); in gk104_clkgate_enable()
46 nvkm_wr32(dev, 0x020288, therm->idle_filter->fecs); in gk104_clkgate_enable()
47 nvkm_wr32(dev, 0x02028c, therm->idle_filter->hubmmu); in gk104_clkgate_enable()
50 for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { in gk104_clkgate_enable()
54 nvkm_mask(dev, 0x20200 + order[i].offset, 0x00ff, 0x0045); in gk104_clkgate_enable()
67 for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { in gk104_clkgate_fini()
71 nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54); in gk104_clkgate_fini()
76 { NVKM_ENGINE_GR, 0, 0x00 },
77 { NVKM_ENGINE_MSPDEC, 0, 0x04 },
[all …]
/Linux-v5.15/drivers/regulator/
Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/Linux-v5.15/drivers/scsi/esas2r/
Datioctl.h58 #define IOCTL_SUCCESS 0
76 * NOTE - if channel == 0xFF, the request is
83 #define FUNC_FW_DOWNLOAD 0x09
84 #define FUNC_FW_UPLOAD 0x12
87 #define FW_IMG_FW 0x01
88 #define FW_IMG_BIOS 0x02
89 #define FW_IMG_NVR 0x03
90 #define FW_IMG_RAW 0x04
91 #define FW_IMG_FM_API 0x05
92 #define FW_IMG_FS_API 0x06
[all …]
/Linux-v5.15/drivers/media/i2c/
Dov5670.c12 #define OV5670_REG_CHIP_ID 0x300a
13 #define OV5670_CHIP_ID 0x005670
15 #define OV5670_REG_MODE_SELECT 0x0100
16 #define OV5670_MODE_STANDBY 0x00
17 #define OV5670_MODE_STREAMING 0x01
19 #define OV5670_REG_SOFTWARE_RST 0x0103
20 #define OV5670_SOFTWARE_RST 0x01
23 #define OV5670_REG_VTS 0x380e
24 #define OV5670_VTS_30FPS 0x0808 /* default for 30 fps */
25 #define OV5670_VTS_MAX 0xffff
[all …]
Dov13858.c16 #define OV13858_REG_MODE_SELECT 0x0100
17 #define OV13858_MODE_STANDBY 0x00
18 #define OV13858_MODE_STREAMING 0x01
20 #define OV13858_REG_SOFTWARE_RST 0x0103
21 #define OV13858_SOFTWARE_RST 0x01
24 #define OV13858_REG_PLL1_CTRL_0 0x0300
25 #define OV13858_REG_PLL1_CTRL_1 0x0301
26 #define OV13858_REG_PLL1_CTRL_2 0x0302
27 #define OV13858_REG_PLL1_CTRL_3 0x0303
28 #define OV13858_REG_PLL1_CTRL_4 0x0304
[all …]
/Linux-v5.15/drivers/gpu/drm/msm/adreno/
Da4xx_gpu.c31 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
62 OUT_RING(ring, 0x00000000); in a4xx_submit()
81 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
82 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
83 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
84 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
85 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
86 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
87 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
88 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]

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