Searched +full:0 +full:x4104000 (Results 1 – 4 of 4) sorted by relevance
45 If present, it restricts the controller to USB2.0 mode of94 reg = <0x00 0x4104000 0x00 0x100>;105 reg = <0x00 0x6000000 0x00 0x10000>,106 <0x00 0x6010000 0x00 0x10000>,107 <0x00 0x6020000 0x00 0x10000>;109 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */111 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
10 #clock-cells = <0>;18 reg = <0x00 0x70000000 0x00 0x100000>;21 ranges = <0x00 0x00 0x70000000 0x100000>;23 atf-sram@0 {24 reg = <0x00 0x20000>;30 reg = <0x00 0x00100000 0x00 0x1c000>;33 ranges = <0x00 0x00 0x00100000 0x1c000>;38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */[all …]
14 #clock-cells = <0>;16 clock-frequency = <0>;20 #clock-cells = <0>;22 clock-frequency = <0>;29 reg = <0x0 0x70000000 0x0 0x800000>;32 ranges = <0x0 0x0 0x70000000 0x800000>;34 atf-sram@0 {35 reg = <0x0 0x20000>;41 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */44 ranges = <0x0 0x0 0x00100000 0x1c000>;[all …]
23 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 0x410000025 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1 0x410000427 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2 0x410000829 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3 0x410000C31 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4 0x410001033 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5 0x410001435 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6 0x410001837 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7 0x410001C39 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8 0x410002041 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_9 0x4100024[all …]
