Searched +full:0 +full:x4100000 (Results 1 – 4 of 4) sorted by relevance
32 const: 075 reg = <0x4100000 0x54>;76 syscon-phy-power = <&scm_conf 0x4000>;77 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;79 #phy-cells = <0>;
13 power-domains = <&k2g_pds 0x0018>;14 clocks = <&k2g_clks 0x0018 0>;17 queue-range = <0 0x80>;18 linkram0 = <0x4020000 0x7ff>;26 managed-queues = <0 0x80>;27 reg = <0x4100000 0x800>,28 <0x4040000 0x100>,29 <0x4080000 0x800>,30 <0x40c0000 0x800>;38 qpend-0 {[all …]
12 reg = <0x0 0x70000000 0x0 0x200000>;15 ranges = <0x0 0x0 0x70000000 0x200000>;17 atf-sram@0 {18 reg = <0x0 0x20000>;22 reg = <0xf0000 0x10000>;26 reg = <0x100000 0x100000>;37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */38 <0x00 0x01880000 0x00 0x90000>, /* GICR */39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */[all …]
23 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 0x410000025 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1 0x410000427 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2 0x410000829 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3 0x410000C31 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4 0x410001033 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5 0x410001435 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6 0x410001837 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7 0x410001C39 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8 0x410002041 #define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_9 0x4100024[all …]
