/Linux-v6.6/drivers/input/touchscreen/ |
D | goodix.h | 13 #define GOODIX_REG_MISCTL_DSP_CTL 0x4010 14 #define GOODIX_REG_MISCTL_SRAM_BANK 0x4048 15 #define GOODIX_REG_MISCTL_MEM_CD_EN 0x4049 16 #define GOODIX_REG_MISCTL_CACHE_EN 0x404B 17 #define GOODIX_REG_MISCTL_TMR0_EN 0x40B0 18 #define GOODIX_REG_MISCTL_SWRST 0x4180 19 #define GOODIX_REG_MISCTL_CPU_SWRST_PULSE 0x4184 20 #define GOODIX_REG_MISCTL_BOOTCTL 0x4190 21 #define GOODIX_REG_MISCTL_BOOT_OPT 0x4218 22 #define GOODIX_REG_MISCTL_BOOT_CTL 0x5094 [all …]
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/Linux-v6.6/drivers/remoteproc/ |
D | mtk_common.h | 15 #define MT8183_SW_RSTN 0x0 16 #define MT8183_SW_RSTN_BIT BIT(0) 17 #define MT8183_SCP_TO_HOST 0x1C 18 #define MT8183_SCP_IPC_INT_BIT BIT(0) 20 #define MT8183_HOST_TO_SCP 0x28 21 #define MT8183_HOST_IPC_INT_BIT BIT(0) 22 #define MT8183_WDT_CFG 0x84 23 #define MT8183_SCP_CLK_SW_SEL 0x4000 24 #define MT8183_SCP_CLK_DIV_SEL 0x4024 25 #define MT8183_SCP_SRAM_PDN 0x402C [all …]
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/Linux-v6.6/Documentation/devicetree/bindings/mfd/ |
D | ti,j721e-system-controller.yaml | 48 "^mux-controller@[0-9a-f]+$": 53 "^clock-controller@[0-9a-f]+$": 59 "phy@[0-9a-f]+$": 65 "^chipid@[0-9a-f]+$": 84 reg = <0x00100000 0x1c000>; 91 reg = <0x00004080 0x50>; 95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ [all …]
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/Linux-v6.6/drivers/gpu/drm/radeon/reg_srcs/ |
D | rv515 | 1 rv515 0x6d40 2 0x1434 SRC_Y_X 3 0x1438 DST_Y_X 4 0x143C DST_HEIGHT_WIDTH 5 0x146C DP_GUI_MASTER_CNTL 6 0x1474 BRUSH_Y_X 7 0x1478 DP_BRUSH_BKGD_CLR 8 0x147C DP_BRUSH_FRGD_CLR 9 0x1480 BRUSH_DATA0 10 0x1484 BRUSH_DATA1 [all …]
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/Linux-v6.6/arch/arm/boot/dts/nxp/mxs/ |
D | imx28-pinfunc.h | 13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 [all …]
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/Linux-v6.6/drivers/net/ethernet/tehuti/ |
D | tehuti.h | 81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff) 83 # define H32_64(x) 0 105 # define NETDEV_TX_OK 0 134 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) 189 * if len == 0 addr is dma 190 * if len != 0 addr is skb */ 207 u64 InUCast; /* 0x7200 */ 208 u64 InMCast; /* 0x7210 */ 209 u64 InBCast; /* 0x7220 */ 210 u64 InPkts; /* 0x7230 */ [all …]
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/Linux-v6.6/drivers/scsi/qla2xxx/ |
D | qla_dbg.c | 13 * | Module Init and Probe | 0x0199 | | 14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff | 15 * | Device Discovery | 0x2134 | 0x2112-0x2115 | 16 * | | | 0x2127-0x2128 | 17 * | Queue Command and IO tracing | 0x3074 | 0x300b | 18 * | | | 0x3027-0x3028 | 19 * | | | 0x303d-0x3041 | 20 * | | | 0x302e,0x3033 | 21 * | | | 0x3036,0x3038 | 22 * | | | 0x303a | [all …]
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/Linux-v6.6/drivers/net/ethernet/renesas/ |
D | rswitch.h | 17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \ 23 for (i--; i >= 0; i--) \ 38 #define RSWITCH_TOP_OFFSET 0x00008000 39 #define RSWITCH_COMA_OFFSET 0x00009000 40 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ 41 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ 42 #define RSWITCH_GWCA0_OFFSET 0x00010000 43 #define RSWITCH_GWCA1_OFFSET 0x00012000 49 #define GWCA_INDEX 0 51 #define GWCA_IPV_NUM 0 [all …]
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/Linux-v6.6/drivers/clk/imx/ |
D | clk-imx8mn.c | 334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe() 343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe() 350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe() 351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe() 352 …hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mn_clocks_probe() 353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe() 354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe() 355 …hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_s… in imx8mn_clocks_probe() 356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe() 357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe() [all …]
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D | clk-imx8mq.c | 299 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe() 309 base = of_iomap(np, 0); in imx8mq_clocks_probe() 314 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 315 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 316 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 317 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe() 318 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe() 319 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe() 320 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe() 321 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe() [all …]
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D | clk-imx8mm.c | 314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe() 323 base = of_iomap(np, 0); in imx8mm_clocks_probe() 328 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe() 329 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe() 330 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe() 331 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe() 332 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 333 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 334 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 335 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe() [all …]
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D | clk-imx8mp.c | 416 anatop_base = devm_of_iomap(dev, np, 0, NULL); in imx8mp_clocks_probe() 422 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe() 433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe() 441 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe() 442 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe() 443 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe() 444 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe() 445 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe() 446 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe() 447 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe() [all …]
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/Linux-v6.6/drivers/clk/qcom/ |
D | mmcc-msm8994.c | 44 { P_XO, 0 }, 54 { P_XO, 0 }, 64 { P_XO, 0 }, 76 { P_XO, 0 }, 91 { 1500000000, 2000000000, 0 }, 95 { 500000000, 1500000000, 0 }, 99 .post_div_mask = 0xf00, 103 .offset = 0x0, 108 .enable_reg = 0x100, 109 .enable_mask = BIT(0), [all …]
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D | mmcc-apq8084.c | 44 .l_reg = 0x0004, 45 .m_reg = 0x0008, 46 .n_reg = 0x000c, 47 .config_reg = 0x0014, 48 .mode_reg = 0x0000, 49 .status_reg = 0x001c, 62 .enable_reg = 0x0100, 63 .enable_mask = BIT(0), 75 .l_reg = 0x0044, 76 .m_reg = 0x0048, [all …]
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D | mmcc-msm8996.c | 64 { 1500000000, 2000000000, 0 }, 70 { 1500000000, 2000000000, 0 }, 74 { 500000000, 1500000000, 0 }, 78 .offset = 0x0, 83 .enable_reg = 0x100, 84 .enable_mask = BIT(0), 97 .offset = 0x0, 112 .offset = 0x30, 117 .enable_reg = 0x100, 131 .offset = 0x30, [all …]
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/Linux-v6.6/drivers/gpu/drm/i915/gt/ |
D | intel_gt_regs.h | 11 #define VLV_GUNIT_BASE 0x180000 25 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) 26 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 27 #define MTL_CC0 0x0 28 #define MTL_CC6 0x3 32 #define RPM_CONFIG0 _MMIO(0xd00) 35 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 38 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SH… 39 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 44 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_… [all …]
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/Linux-v6.6/tools/perf/pmu-events/arch/powerpc/power9/ |
D | other.json | 3 "EventCode": "0x3084", 8 "EventCode": "0xF880", 13 "EventCode": "0x4088", 18 "EventCode": "0x20A4", 23 "EventCode": "0x40008", 28 "EventCode": "0x20064", 33 "EventCode": "0x260B4", 38 "EventCode": "0x20006", 43 "EventCode": "0x201E4", 48 "EventCode": "0x4E044", [all …]
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/Linux-v6.6/drivers/pinctrl/tegra/ |
D | pinctrl-tegra234.c | 1433 .mux_bit = 0, \ 1447 #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1448 #define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1449 #define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1450 #define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1451 #define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1452 #define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1453 #define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1454 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1455 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0) [all …]
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/Linux-v6.6/sound/soc/mediatek/mt8195/ |
D | mt8195-reg.h | 13 #define AFE_SRAM_BASE (0x10880000) 14 #define AFE_SRAM_SIZE (0x10000) 16 #define AUDIO_TOP_CON0 (0x0000) 17 #define AUDIO_TOP_CON1 (0x0004) 18 #define AUDIO_TOP_CON2 (0x0008) 19 #define AUDIO_TOP_CON3 (0x000c) 20 #define AUDIO_TOP_CON4 (0x0010) 21 #define AUDIO_TOP_CON5 (0x0014) 22 #define AUDIO_TOP_CON6 (0x0018) 23 #define AFE_MAS_HADDR_MSB (0x0020) [all …]
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/Linux-v6.6/sound/soc/mediatek/mt8188/ |
D | mt8188-reg.h | 14 #define AUDIO_TOP_CON0 (0x0000) 15 #define AUDIO_TOP_CON1 (0x0004) 16 #define AUDIO_TOP_CON2 (0x0008) 17 #define AUDIO_TOP_CON3 (0x000c) 18 #define AUDIO_TOP_CON4 (0x0010) 19 #define AUDIO_TOP_CON5 (0x0014) 20 #define AUDIO_TOP_CON6 (0x0018) 21 #define AFE_MAS_HADDR_MSB (0x0020) 22 #define AFE_MEMIF_ONE_HEART (0x0024) 23 #define AFE_MUX_SEL_CFG (0x0044) [all …]
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/Linux-v6.6/arch/arm64/boot/dts/ti/ |
D | k3-j721e-main.dtsi | 15 #clock-cells = <0>; 17 clock-frequency = <0>; 21 #clock-cells = <0>; 23 clock-frequency = <0>; 30 reg = <0x0 0x70000000 0x0 0x800000>; 33 ranges = <0x0 0x0 0x70000000 0x800000>; 35 atf-sram@0 { 36 reg = <0x0 0x20000>; 42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 45 ranges = <0x0 0x0 0x00100000 0x1c000>; [all …]
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/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dce/ |
D | dce_6_0_d.h | 26 #define ixATTR00 0x0000 27 #define ixATTR01 0x0001 28 #define ixATTR02 0x0002 29 #define ixATTR03 0x0003 30 #define ixATTR04 0x0004 31 #define ixATTR05 0x0005 32 #define ixATTR06 0x0006 33 #define ixATTR07 0x0007 34 #define ixATTR08 0x0008 35 #define ixATTR09 0x0009 [all …]
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D | dce_8_0_d.h | 27 #define mmPIPE0_PG_CONFIG 0x1760 28 #define mmPIPE0_PG_ENABLE 0x1761 29 #define mmPIPE0_PG_STATUS 0x1762 30 #define mmPIPE1_PG_CONFIG 0x1764 31 #define mmPIPE1_PG_ENABLE 0x1765 32 #define mmPIPE1_PG_STATUS 0x1766 33 #define mmPIPE2_PG_CONFIG 0x1768 34 #define mmPIPE2_PG_ENABLE 0x1769 35 #define mmPIPE2_PG_STATUS 0x176a 36 #define mmPIPE3_PG_CONFIG 0x176c [all …]
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D | dce_11_0_d.h | 27 #define mmPIPE0_PG_CONFIG 0x2c0 28 #define mmPIPE0_PG_ENABLE 0x2c1 29 #define mmPIPE0_PG_STATUS 0x2c2 30 #define mmPIPE1_PG_CONFIG 0x2c3 31 #define mmPIPE1_PG_ENABLE 0x2c4 32 #define mmPIPE1_PG_STATUS 0x2c5 33 #define mmPIPE2_PG_CONFIG 0x2c6 34 #define mmPIPE2_PG_ENABLE 0x2c7 35 #define mmPIPE2_PG_STATUS 0x2c8 36 #define mmDCFEV0_PG_CONFIG 0x2db [all …]
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/Linux-v6.6/tools/perf/pmu-events/arch/powerpc/power8/ |
D | other.json | 3 "EventCode": "0x1f05e", 9 "EventCode": "0x2006e", 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 15 "EventCode": "0x4e05e", 17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel… 21 "EventCode": "0x610050", 27 "EventCode": "0x520050", 33 "EventCode": "0x620052", 39 "EventCode": "0x610052", 45 "EventCode": "0x610054", [all …]
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