/Linux-v6.6/Documentation/devicetree/bindings/mfd/ |
D | ti,j721e-system-controller.yaml | 48 "^mux-controller@[0-9a-f]+$": 53 "^clock-controller@[0-9a-f]+$": 59 "phy@[0-9a-f]+$": 65 "^chipid@[0-9a-f]+$": 84 reg = <0x00100000 0x1c000>; 91 reg = <0x00004080 0x50>; 95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ [all …]
|
/Linux-v6.6/include/linux/mfd/wm831x/ |
D | core.h | 25 #define WM831X_RESET_ID 0x00 26 #define WM831X_REVISION 0x01 27 #define WM831X_PARENT_ID 0x4000 28 #define WM831X_SYSVDD_CONTROL 0x4001 29 #define WM831X_THERMAL_MONITORING 0x4002 30 #define WM831X_POWER_STATE 0x4003 31 #define WM831X_WATCHDOG 0x4004 32 #define WM831X_ON_PIN_CONTROL 0x4005 33 #define WM831X_RESET_CONTROL 0x4006 34 #define WM831X_CONTROL_INTERFACE 0x4007 [all …]
|
/Linux-v6.6/drivers/gpu/drm/radeon/reg_srcs/ |
D | rv515 | 1 rv515 0x6d40 2 0x1434 SRC_Y_X 3 0x1438 DST_Y_X 4 0x143C DST_HEIGHT_WIDTH 5 0x146C DP_GUI_MASTER_CNTL 6 0x1474 BRUSH_Y_X 7 0x1478 DP_BRUSH_BKGD_CLR 8 0x147C DP_BRUSH_FRGD_CLR 9 0x1480 BRUSH_DATA0 10 0x1484 BRUSH_DATA1 [all …]
|
/Linux-v6.6/drivers/scsi/ |
D | hptiop.h | 30 #define IOPMU_QUEUE_EMPTY 0xffffffff 31 #define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000 32 #define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000 33 #define IOPMU_QUEUE_REQUEST_SIZE_BIT 0x40000000 34 #define IOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000 40 #define IOPMU_OUTBOUND_INT_PCI 0x10 46 #define IOPMU_INBOUND_INT_POSTQUEUE 0x10 63 __le32 reserved[0x20400 / 4]; 72 __le32 reserved0[(0x4000 - 0) / 4]; 75 __le32 reserved1[(0x4018 - 0x4008) / 4]; [all …]
|
/Linux-v6.6/arch/arm/boot/dts/nxp/mxs/ |
D | imx28-pinfunc.h | 13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 [all …]
|
/Linux-v6.6/sound/pci/hda/ |
D | hp_x360_helper.c | 10 { 0x17, 0x90170110 }, in alc295_fixup_hp_top_speakers() 14 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0000), WRITE_COEF(0x28, 0x0000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() 15 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x003f), WRITE_COEF(0x28, 0x1000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() 16 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0004), WRITE_COEF(0x28, 0x0600), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() 17 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006a), WRITE_COEF(0x28, 0x0006), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() 18 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006c), WRITE_COEF(0x28, 0xc0c0), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() 19 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0008), WRITE_COEF(0x28, 0xb000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() 20 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x002e), WRITE_COEF(0x28, 0x0800), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() 21 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006a), WRITE_COEF(0x28, 0x00c1), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() 22 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006c), WRITE_COEF(0x28, 0x0320), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers() [all …]
|
/Linux-v6.6/drivers/video/fbdev/ |
D | hpfb.c | 34 #define TC_NBLANK 0x4080 35 #define TC_WEN 0x4088 36 #define TC_REN 0x408c 37 #define TC_FBEN 0x4090 38 #define TC_PRR 0x40ea 41 #define RR_CLEAR 0x0 42 #define RR_COPY 0x3 43 #define RR_NOOP 0x5 44 #define RR_XOR 0x6 45 #define RR_INVERT 0xa [all …]
|
/Linux-v6.6/drivers/net/ethernet/tehuti/ |
D | tehuti.h | 81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff) 83 # define H32_64(x) 0 105 # define NETDEV_TX_OK 0 134 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) 189 * if len == 0 addr is dma 190 * if len != 0 addr is skb */ 207 u64 InUCast; /* 0x7200 */ 208 u64 InMCast; /* 0x7210 */ 209 u64 InBCast; /* 0x7220 */ 210 u64 InPkts; /* 0x7230 */ [all …]
|
/Linux-v6.6/drivers/net/ethernet/agere/ |
D | et131x.h | 53 #define LBCIF_DWORD0_GROUP 0xAC 54 #define LBCIF_DWORD1_GROUP 0xB0 57 #define LBCIF_ADDRESS_REGISTER 0xAC 58 #define LBCIF_DATA_REGISTER 0xB0 59 #define LBCIF_CONTROL_REGISTER 0xB1 60 #define LBCIF_STATUS_REGISTER 0xB2 63 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 64 #define LBCIF_CONTROL_PAGE_WRITE 0x02 65 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08 66 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 [all …]
|
/Linux-v6.6/drivers/net/wireless/ath/ath9k/ |
D | reg.h | 22 #define AR_CR 0x0008 23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004) 24 #define AR_CR_RXD 0x00000020 25 #define AR_CR_SWI 0x00000040 27 #define AR_RXDP 0x000C 29 #define AR_CFG 0x0014 30 #define AR_CFG_SWTD 0x00000001 31 #define AR_CFG_SWTB 0x00000002 32 #define AR_CFG_SWRD 0x00000004 33 #define AR_CFG_SWRB 0x00000008 [all …]
|
/Linux-v6.6/drivers/scsi/qla2xxx/ |
D | qla_dbg.c | 13 * | Module Init and Probe | 0x0199 | | 14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff | 15 * | Device Discovery | 0x2134 | 0x2112-0x2115 | 16 * | | | 0x2127-0x2128 | 17 * | Queue Command and IO tracing | 0x3074 | 0x300b | 18 * | | | 0x3027-0x3028 | 19 * | | | 0x303d-0x3041 | 20 * | | | 0x302e,0x3033 | 21 * | | | 0x3036,0x3038 | 22 * | | | 0x303a | [all …]
|
/Linux-v6.6/drivers/net/ethernet/renesas/ |
D | rswitch.h | 17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \ 23 for (i--; i >= 0; i--) \ 38 #define RSWITCH_TOP_OFFSET 0x00008000 39 #define RSWITCH_COMA_OFFSET 0x00009000 40 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ 41 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ 42 #define RSWITCH_GWCA0_OFFSET 0x00010000 43 #define RSWITCH_GWCA1_OFFSET 0x00012000 49 #define GWCA_INDEX 0 51 #define GWCA_IPV_NUM 0 [all …]
|
/Linux-v6.6/sound/soc/codecs/ |
D | rt1305.c | 31 #define RT1305_PR_RANGE_BASE (0xff + 1) 32 #define RT1305_PR_SPACING 0x100 34 #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING)) 41 .range_max = RT1305_PR_BASE + 0xff, 43 .selector_mask = 0xff, 44 .selector_shift = 0x0, 46 .window_len = 0x1, 53 { RT1305_PR_BASE + 0xcf, 0x5548 }, 54 { RT1305_PR_BASE + 0x5d, 0x0442 }, 55 { RT1305_PR_BASE + 0xc1, 0x0320 }, [all …]
|
/Linux-v6.6/drivers/clk/imx/ |
D | clk-imx8mn.c | 334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe() 343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe() 350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe() 351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe() 352 …hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mn_clocks_probe() 353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe() 354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe() 355 …hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_s… in imx8mn_clocks_probe() 356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe() 357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe() [all …]
|
D | clk-imx8mq.c | 299 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe() 309 base = of_iomap(np, 0); in imx8mq_clocks_probe() 314 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 315 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 316 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 317 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe() 318 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe() 319 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe() 320 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe() 321 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe() [all …]
|
D | clk-imx8mm.c | 314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe() 323 base = of_iomap(np, 0); in imx8mm_clocks_probe() 328 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe() 329 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe() 330 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe() 331 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe() 332 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 333 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 334 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 335 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe() [all …]
|
D | clk-imx8mp.c | 416 anatop_base = devm_of_iomap(dev, np, 0, NULL); in imx8mp_clocks_probe() 422 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe() 433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe() 441 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe() 442 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe() 443 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe() 444 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe() 445 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe() 446 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe() 447 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe() [all …]
|
/Linux-v6.6/drivers/net/ethernet/marvell/octeontx2/af/ |
D | rvu_reg.h | 12 #define RVU_AF_MSIXTR_BASE (0x10) 13 #define RVU_AF_ECO (0x20) 14 #define RVU_AF_BLK_RST (0x30) 15 #define RVU_AF_PF_BAR4_ADDR (0x40) 16 #define RVU_AF_RAS (0x100) 17 #define RVU_AF_RAS_W1S (0x108) 18 #define RVU_AF_RAS_ENA_W1S (0x110) 19 #define RVU_AF_RAS_ENA_W1C (0x118) 20 #define RVU_AF_GEN_INT (0x120) 21 #define RVU_AF_GEN_INT_W1S (0x128) [all …]
|
/Linux-v6.6/arch/arm64/boot/dts/ti/ |
D | k3-am65-main.dtsi | 12 reg = <0x0 0x70000000 0x0 0x200000>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 22 reg = <0xf0000 0x10000>; 26 reg = <0x100000 0x100000>; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ [all …]
|
/Linux-v6.6/drivers/gpu/drm/i915/gt/ |
D | intel_gt_regs.h | 11 #define VLV_GUNIT_BASE 0x180000 25 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) 26 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 27 #define MTL_CC0 0x0 28 #define MTL_CC6 0x3 32 #define RPM_CONFIG0 _MMIO(0xd00) 35 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 38 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SH… 39 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 44 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_… [all …]
|
/Linux-v6.6/tools/perf/pmu-events/arch/powerpc/power9/ |
D | other.json | 3 "EventCode": "0x3084", 8 "EventCode": "0xF880", 13 "EventCode": "0x4088", 18 "EventCode": "0x20A4", 23 "EventCode": "0x40008", 28 "EventCode": "0x20064", 33 "EventCode": "0x260B4", 38 "EventCode": "0x20006", 43 "EventCode": "0x201E4", 48 "EventCode": "0x4E044", [all …]
|
/Linux-v6.6/drivers/clk/qcom/ |
D | mmcc-msm8994.c | 44 { P_XO, 0 }, 54 { P_XO, 0 }, 64 { P_XO, 0 }, 76 { P_XO, 0 }, 91 { 1500000000, 2000000000, 0 }, 95 { 500000000, 1500000000, 0 }, 99 .post_div_mask = 0xf00, 103 .offset = 0x0, 108 .enable_reg = 0x100, 109 .enable_mask = BIT(0), [all …]
|
D | mmcc-apq8084.c | 44 .l_reg = 0x0004, 45 .m_reg = 0x0008, 46 .n_reg = 0x000c, 47 .config_reg = 0x0014, 48 .mode_reg = 0x0000, 49 .status_reg = 0x001c, 62 .enable_reg = 0x0100, 63 .enable_mask = BIT(0), 75 .l_reg = 0x0044, 76 .m_reg = 0x0048, [all …]
|
/Linux-v6.6/drivers/pinctrl/tegra/ |
D | pinctrl-tegra234.c | 1433 .mux_bit = 0, \ 1447 #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1448 #define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1449 #define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1450 #define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1451 #define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1452 #define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1453 #define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1454 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1455 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0) [all …]
|
/Linux-v6.6/sound/soc/mediatek/mt8195/ |
D | mt8195-reg.h | 13 #define AFE_SRAM_BASE (0x10880000) 14 #define AFE_SRAM_SIZE (0x10000) 16 #define AUDIO_TOP_CON0 (0x0000) 17 #define AUDIO_TOP_CON1 (0x0004) 18 #define AUDIO_TOP_CON2 (0x0008) 19 #define AUDIO_TOP_CON3 (0x000c) 20 #define AUDIO_TOP_CON4 (0x0010) 21 #define AUDIO_TOP_CON5 (0x0014) 22 #define AUDIO_TOP_CON6 (0x0018) 23 #define AFE_MAS_HADDR_MSB (0x0020) [all …]
|