/Linux-v6.6/drivers/gpu/host1x/hw/ |
D | hw_host1x08_common.h | 6 #define HOST1X_COMMON_OFA_MLOCK 0x4050 7 #define HOST1X_COMMON_NVJPG1_MLOCK 0x4070 8 #define HOST1X_COMMON_VIC_MLOCK 0x4078 9 #define HOST1X_COMMON_NVENC_MLOCK 0x407c 10 #define HOST1X_COMMON_NVDEC_MLOCK 0x4080 11 #define HOST1X_COMMON_NVJPG_MLOCK 0x4084
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/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/ |
D | jpeg_v4_0_3.h | 27 #define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff 28 #define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d 29 #define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e 30 #define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f 31 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab 32 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac 33 #define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4 34 #define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6 35 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6 36 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7 [all …]
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D | jpeg_v2_0.h | 27 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff 28 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029 29 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a 30 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b 31 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea 32 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb 33 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf 34 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1 35 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8 36 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9 [all …]
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/Linux-v6.6/drivers/remoteproc/ |
D | mtk_common.h | 15 #define MT8183_SW_RSTN 0x0 16 #define MT8183_SW_RSTN_BIT BIT(0) 17 #define MT8183_SCP_TO_HOST 0x1C 18 #define MT8183_SCP_IPC_INT_BIT BIT(0) 20 #define MT8183_HOST_TO_SCP 0x28 21 #define MT8183_HOST_IPC_INT_BIT BIT(0) 22 #define MT8183_WDT_CFG 0x84 23 #define MT8183_SCP_CLK_SW_SEL 0x4000 24 #define MT8183_SCP_CLK_DIV_SEL 0x4024 25 #define MT8183_SCP_SRAM_PDN 0x402C [all …]
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/Linux-v6.6/Documentation/devicetree/bindings/mfd/ |
D | ti,j721e-system-controller.yaml | 48 "^mux-controller@[0-9a-f]+$": 53 "^clock-controller@[0-9a-f]+$": 59 "phy@[0-9a-f]+$": 65 "^chipid@[0-9a-f]+$": 84 reg = <0x00100000 0x1c000>; 91 reg = <0x00004080 0x50>; 95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ [all …]
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/Linux-v6.6/drivers/dma/xilinx/ |
D | xdma-regs.h | 32 #define XDMA_DESC_MAGIC 0xad4bUL 34 #define XDMA_DESC_FLAGS_BITS GENMASK(7, 0) 35 #define XDMA_DESC_STOPPED BIT(0) 72 #define XDMA_CHAN_IDENTIFIER 0x0 73 #define XDMA_CHAN_CONTROL 0x4 74 #define XDMA_CHAN_CONTROL_W1S 0x8 75 #define XDMA_CHAN_CONTROL_W1C 0xc 76 #define XDMA_CHAN_STATUS 0x40 77 #define XDMA_CHAN_COMPLETED_DESC 0x48 78 #define XDMA_CHAN_ALIGNMENTS 0x4c [all …]
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/Linux-v6.6/lib/ |
D | crc-itu-t.c | 10 /* CRC table for the CRC ITU-T V.41 0x1021 (x^16 + x^12 + x^5 + 1) */ 12 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 13 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, 14 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, 15 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 16 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, 17 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, 18 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, 19 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, 20 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, [all …]
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D | crc-ccitt.c | 13 * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12. 17 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 18 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 19 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 20 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 21 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, 22 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, 23 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, 24 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, 25 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, [all …]
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/Linux-v6.6/drivers/gpu/drm/radeon/reg_srcs/ |
D | rv515 | 1 rv515 0x6d40 2 0x1434 SRC_Y_X 3 0x1438 DST_Y_X 4 0x143C DST_HEIGHT_WIDTH 5 0x146C DP_GUI_MASTER_CNTL 6 0x1474 BRUSH_Y_X 7 0x1478 DP_BRUSH_BKGD_CLR 8 0x147C DP_BRUSH_FRGD_CLR 9 0x1480 BRUSH_DATA0 10 0x1484 BRUSH_DATA1 [all …]
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/Linux-v6.6/drivers/net/ethernet/chelsio/cxgb4/ |
D | t4_pci_id_tbl.h | 46 * -- The PCI Function Number to use in the PCI Device ID Table. "0" 73 /* T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where: 76 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs 97 CH_PCI_ID_TABLE_FENTRY(0x4000), /* T440-dbg */ 98 CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */ 99 CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */ 100 CH_PCI_ID_TABLE_FENTRY(0x4003), /* T440-cr */ 101 CH_PCI_ID_TABLE_FENTRY(0x4004), /* T420-bch */ 102 CH_PCI_ID_TABLE_FENTRY(0x4005), /* T440-bch */ 103 CH_PCI_ID_TABLE_FENTRY(0x4006), /* T440-ch */ [all …]
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/Linux-v6.6/include/linux/mfd/wm831x/ |
D | core.h | 25 #define WM831X_RESET_ID 0x00 26 #define WM831X_REVISION 0x01 27 #define WM831X_PARENT_ID 0x4000 28 #define WM831X_SYSVDD_CONTROL 0x4001 29 #define WM831X_THERMAL_MONITORING 0x4002 30 #define WM831X_POWER_STATE 0x4003 31 #define WM831X_WATCHDOG 0x4004 32 #define WM831X_ON_PIN_CONTROL 0x4005 33 #define WM831X_RESET_CONTROL 0x4006 34 #define WM831X_CONTROL_INTERFACE 0x4007 [all …]
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D | regulator.h | 14 * R16462 (0x404E) - Current Sink 1 16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */ 17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */ 20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */ 21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */ 24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */ 25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */ 28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */ 31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */ 34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */ [all …]
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/Linux-v6.6/drivers/net/wireless/mediatek/mt7601u/ |
D | regs.h | 12 #define MT_ASIC_VERSION 0x0000 14 #define MT76XX_REV_E3 0x22 15 #define MT76XX_REV_E4 0x33 17 #define MT_CMB_CTRL 0x0020 21 #define MT_EFUSE_CTRL 0x0024 22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0) 30 #define MT_EFUSE_DATA_BASE 0x0028 33 #define MT_COEXCFG0 0x0040 34 #define MT_COEXCFG0_COEX_EN BIT(0) 36 #define MT_WLAN_FUN_CTRL 0x0080 [all …]
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/Linux-v6.6/drivers/net/ethernet/agere/ |
D | et131x.h | 53 #define LBCIF_DWORD0_GROUP 0xAC 54 #define LBCIF_DWORD1_GROUP 0xB0 57 #define LBCIF_ADDRESS_REGISTER 0xAC 58 #define LBCIF_DATA_REGISTER 0xB0 59 #define LBCIF_CONTROL_REGISTER 0xB1 60 #define LBCIF_STATUS_REGISTER 0xB2 63 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 64 #define LBCIF_CONTROL_PAGE_WRITE 0x02 65 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08 66 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 [all …]
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/Linux-v6.6/drivers/video/fbdev/ |
D | gxt4500.c | 19 #define PCI_DEVICE_ID_IBM_GXT4500P 0x21c 20 #define PCI_DEVICE_ID_IBM_GXT6500P 0x21b 21 #define PCI_DEVICE_ID_IBM_GXT4000P 0x16e 22 #define PCI_DEVICE_ID_IBM_GXT6000P 0x170 27 #define CFG_ENDIAN0 0x40 30 #define STATUS 0x1000 31 #define CTRL_REG0 0x1004 32 #define CR0_HALT_DMA 0x4 33 #define CR0_RASTER_RESET 0x8 34 #define CR0_GEOM_RESET 0x10 [all …]
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/Linux-v6.6/drivers/clk/qcom/ |
D | mmcc-apq8084.c | 44 .l_reg = 0x0004, 45 .m_reg = 0x0008, 46 .n_reg = 0x000c, 47 .config_reg = 0x0014, 48 .mode_reg = 0x0000, 49 .status_reg = 0x001c, 62 .enable_reg = 0x0100, 63 .enable_mask = BIT(0), 75 .l_reg = 0x0044, 76 .m_reg = 0x0048, [all …]
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D | camcc-sc7180.c | 35 { 600000000, 3300000000UL, 0 }, 39 { 249600000, 2000000000UL, 0 }, 44 .l = 0x1f, 45 .alpha = 0x4000, 46 .config_ctl_val = 0x20485699, 47 .config_ctl_hi_val = 0x00002067, 48 .test_ctl_val = 0x40000000, 49 .user_ctl_hi_val = 0x00004805, 50 .user_ctl_val = 0x00000001, 54 .offset = 0x0, [all …]
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D | mmcc-msm8996.c | 64 { 1500000000, 2000000000, 0 }, 70 { 1500000000, 2000000000, 0 }, 74 { 500000000, 1500000000, 0 }, 78 .offset = 0x0, 83 .enable_reg = 0x100, 84 .enable_mask = BIT(0), 97 .offset = 0x0, 112 .offset = 0x30, 117 .enable_reg = 0x100, 131 .offset = 0x30, [all …]
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D | camcc-sm6350.c | 36 { 249600000, 2000000000, 0 }, 41 .l = 0x1f, 42 .alpha = 0x4000, 43 .config_ctl_val = 0x20485699, 44 .config_ctl_hi_val = 0x00002067, 45 .test_ctl_val = 0x40000000, 46 .test_ctl_hi_val = 0x00000002, 47 .user_ctl_val = 0x00000101, 48 .user_ctl_hi_val = 0x00004805, 52 .offset = 0x0, [all …]
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/Linux-v6.6/drivers/media/i2c/ |
D | adv7180.c | 25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 29 #define ADV7180_STD_NTSC_J 0x4 30 #define ADV7180_STD_NTSC_M 0x5 31 #define ADV7180_STD_PAL60 0x6 32 #define ADV7180_STD_NTSC_443 0x7 33 #define ADV7180_STD_PAL_BG 0x8 34 #define ADV7180_STD_PAL_N 0x9 [all …]
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/Linux-v6.6/drivers/net/wireless/microchip/wilc1000/ |
D | wlan_if.h | 22 WILC_FW_BSS_TYPE_INFRA = 0, 28 WILC_FW_OPER_MODE_B_ONLY = 0, /* 1, 2 M, otherwise 5, 11 M */ 35 WILC_FW_PREAMBLE_SHORT = 0, /* Short Preamble */ 41 WILC_FW_PASSIVE_SCAN = 0, 46 WILC_FW_NO_POWERSAVE = 0, 54 WILC_BUS_ACQUIRE_ONLY = 0, 59 WILC_BUS_RELEASE_ONLY = 0, 64 WILC_FW_NO_ENCRYPT = 0, 65 WILC_FW_ENCRYPT_ENABLED = BIT(0), 97 WILC_FW_MFP_NONE = 0x0, [all …]
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/Linux-v6.6/drivers/pci/controller/ |
D | pcie-brcmstb.c | 38 #define BRCM_PCIE_CAP_REGS 0x00ac 41 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc 43 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 45 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c 46 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff 48 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc 49 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 51 #define PCIE_RC_DL_MDIO_ADDR 0x1100 52 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 [all …]
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/Linux-v6.6/drivers/net/wireless/ath/ath9k/ |
D | reg.h | 22 #define AR_CR 0x0008 23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004) 24 #define AR_CR_RXD 0x00000020 25 #define AR_CR_SWI 0x00000040 27 #define AR_RXDP 0x000C 29 #define AR_CFG 0x0014 30 #define AR_CFG_SWTD 0x00000001 31 #define AR_CFG_SWTB 0x00000002 32 #define AR_CFG_SWRD 0x00000004 33 #define AR_CFG_SWRB 0x00000008 [all …]
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/Linux-v6.6/arch/arm64/boot/dts/ti/ |
D | k3-j7200-main.dtsi | 10 #clock-cells = <0>; 18 reg = <0x00 0x70000000 0x00 0x100000>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 45 reg = <0x4044 0x10>; [all …]
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/Linux-v6.6/drivers/pci/switch/ |
D | switchtec.c | 44 MRPC_IDLE = 0, 171 memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE); in mrpc_cmd_submit() 199 return 0; in mrpc_queue_cmd() 213 stdev->mrpc_busy = 0; in mrpc_cleanup_cmd() 239 stuser->return_code = 0; in mrpc_complete_cmd() 249 if (stuser->return_code != 0) in mrpc_complete_cmd() 354 buf[len + 1] = 0; in io_string_show() 356 for (i = len - 1; i > 0; i--) { in io_string_show() 360 buf[i + 1] = 0; in io_string_show() 481 return 0; in switchtec_dev_open() [all …]
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