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/Linux-v5.10/arch/xtensa/boot/dts/
Dkc705.dts9 …earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw…
11 memory@0 {
13 reg = <0x00000000 0x38000000>;
25 size = <0x04000000>;
26 alignment = <0x2000>;
27 alloc-ranges = <0x00000000 0x20000000>;
/Linux-v5.10/Documentation/devicetree/bindings/pci/
Drcar-pci.txt55 reg = <0 0xfe000000 0 0x80000>;
58 bus-range = <0x00 0xff>;
60 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
61 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
62 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
63 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
64 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
65 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
66 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
68 interrupt-map-mask = <0 0 0 0>;
[all …]
Drcar-pci-ep.yaml72 reg = <0xfe000000 0x80000>,
73 <0xfe100000 0x100000>,
74 <0xfe200000 0x200000>,
75 <0x30000000 0x8000000>,
76 <0x38000000 0x8000000>;
/Linux-v5.10/arch/arm64/boot/dts/renesas/
Dr8a77950-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x5 0x00000000 0x0 0x40000000>;
30 reg = <0x6 0x00000000 0x0 0x40000000>;
35 reg = <0x7 0x00000000 0x0 0x40000000>;
Dr8a77960-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x6 0x00000000 0x0 0x40000000>;
36 clock-names = "du.0", "du.1", "du.2",
37 "dclkin.0", "dclkin.1", "dclkin.2";
Dr8a77951-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x5 0x00000000 0x0 0x40000000>;
30 reg = <0x6 0x00000000 0x0 0x40000000>;
35 reg = <0x7 0x00000000 0x0 0x40000000>;
48 clock-names = "du.0", "du.1", "du.2", "du.3",
49 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
Dr8a77951-salvator-x.dts3 * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
153 pinctrl-0 = <&usb2_pins>;
Dr8a77950-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
153 pinctrl-0 = <&usb2_pins>;
Dr8a77951-salvator-xs.dts3 * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
138 * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
144 * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
195 pinctrl-0 = <&usb2_pins>;
[all …]
Dr8a77970-eagle.dts53 #size-cells = <0>;
55 port@0 {
56 reg = <0>;
74 reg = <0x0 0x48000000 0x0 0x38000000>;
79 pinctrl-0 = <&avb_pins>;
87 phy0: ethernet-phy@0 {
89 reg = <0>;
96 pinctrl-0 = <&canfd0_pins>;
118 pinctrl-0 = <&i2c0_pins>;
126 reg = <0x20>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/arm/stm32/
Dst,mlahb.yaml61 reg = <0x10000000 0x40000>;
63 dma-ranges = <0x00000000 0x38000000 0x10000>,
64 <0x10000000 0x10000000 0x60000>,
65 <0x30000000 0x30000000 0x60000>;
68 reg = <0x10000000 0x40000>;
/Linux-v5.10/arch/xtensa/configs/
Dxip_kc705_defconfig23 CONFIG_XIP_DATA_ADDR=0xd0000000
24 CONFIG_KERNEL_VIRTUAL_ADDRESS=0xe6000000
25 CONFIG_KERNEL_LOAD_ADDRESS=0xf6000000
30 …arlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw …
Dgeneric_kc705_defconfig31 …arlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw …
Daudio_kc705_defconfig32 …arlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw …
/Linux-v5.10/arch/sparc/include/asm/
Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dethernut5.dts19 reg = <0x20000000 0x08000000>;
39 timer@0 {
41 reg = <0>, <1>;
74 pinctrl-0 = <&pinctrl_nand_cs>;
78 reg = <0x3 0x0 0x800000>;
90 root@0 {
92 reg = <0x0 0x08000000>;
97 reg = <0x08000000 0x38000000>;
110 i2c-gpio-0 {
115 reg = <0x51>;
Dstm32mp15xx-osd32.dtsi19 reg = <0x10000000 0x40000>;
25 reg = <0x10040000 0x1000>;
31 reg = <0x10041000 0x1000>;
37 reg = <0x10042000 0x4000>;
43 reg = <0x30000000 0x40000>;
49 reg = <0x38000000 0x10000>;
63 pinctrl-0 = <&i2c4_pins_a>;
72 reg = <0x33>;
73 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
89 regulator-initial-mode = <0>;
[all …]
/Linux-v5.10/sound/soc/mxs/
Dmxs-saif.h10 #define SAIF_CTRL 0x0
11 #define SAIF_STAT 0x10
12 #define SAIF_DATA 0x20
13 #define SAIF_VERSION 0X30
16 #define BM_SAIF_CTRL_SFTRST 0x80000000
17 #define BM_SAIF_CTRL_CLKGATE 0x40000000
19 #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
22 #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
23 #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
24 #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
[all …]
/Linux-v5.10/arch/arm/mach-s3c/
Dmap-s3c64xx.h22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
Dmap-s3c24xx.h19 #define S3C2410_PA_IRQ (0x4A000000)
23 #define S3C2410_PA_MEMCTRL (0x48000000)
27 #define S3C2410_PA_TIMER (0x51000000)
34 #define S3C2410_PA_USBDEV (0x52000000)
38 #define S3C2410_PA_WATCHDOG (0x53000000)
52 #define S3C2410_PA_USBHOST (0x49000000)
55 #define S3C2416_PA_HSUDC (0x49800000)
59 #define S3C2410_PA_DMA (0x4B000000)
63 #define S3C2410_PA_CLKPWR (0x4C000000)
66 #define S3C2410_PA_LCD (0x4D000000)
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/soc/ti/
Dk3-ringacc.yaml85 reg = <0x0 0x3c000000 0x0 0x400000>,
86 <0x0 0x38000000 0x0 0x400000>,
87 <0x0 0x31120000 0x0 0x100>,
88 <0x0 0x33000000 0x0 0x40000>;
91 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
/Linux-v5.10/Documentation/devicetree/bindings/remoteproc/
Dst,stm32-rproc.yaml119 reg = <0x10000000 0x40000>,
120 <0x30000000 0x40000>,
121 <0x38000000 0x10000>;
123 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
124 st,syscfg-tz = <&rcc 0x000 0x1>;
/Linux-v5.10/arch/riscv/boot/dts/kendryte/
Dk210.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0>;
37 i-cache-size = <0x8000>;
39 d-cache-size = <0x8000>;
55 i-cache-size = <0x8000>;
57 d-cache-size = <0x8000>;
71 reg = <0x80000000 0x400000>,
72 <0x80400000 0x200000>,
73 <0x80600000 0x200000>;
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddacnv50.c33 nvkm_mask(device, 0x614280 + doff, 0x07070707, 0x00000000); in nv50_dac_clock()
44 nvkm_wr32(device, 0x61a00c + doff, 0x00100000 | loadval); in nv50_dac_sense()
47 loadval = nvkm_mask(device, 0x61a00c + doff, 0xffffffff, 0x00000000); in nv50_dac_sense()
50 if (!(loadval & 0x80000000)) in nv50_dac_sense()
53 return (loadval & 0x38000000) >> 27; in nv50_dac_sense()
60 if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000)) in nv50_dac_power_wait()
71 const u32 shift = normal ? 0 : 16; in nv50_dac_power()
72 const u32 state = 0x80000000 | (0x00000040 * ! pu | in nv50_dac_power()
73 0x00000010 * ! data | in nv50_dac_power()
74 0x00000004 * ! vsync | in nv50_dac_power()
[all …]
/Linux-v5.10/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_io.h8 * Physical memory map, RAM is mapped at 0x0.
12 #define BCM_PCMCIA_COMMON_BASE_PA (0x20000000)
17 #define BCM_PCMCIA_ATTR_BASE_PA (0x21000000)
22 #define BCM_PCMCIA_IO_BASE_PA (0x22000000)
27 #define BCM_PCI_MEM_BASE_PA (0x30000000)
32 #define BCM_PCI_IO_BASE_PA (0x08000000)
39 #define BCM_CB_MEM_BASE_PA (0x38000000)
44 #define BCM_PCIE_MEM_BASE_PA 0x10f00000

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