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12

/Linux-v6.1/drivers/misc/habanalabs/include/goya/asic_reg/
Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Damlogic,meson-g12a-usb2-phy.yaml37 const: 0
72 reg = <0x36000 0x2000>;
77 #phy-cells = <0>;
/Linux-v6.1/Documentation/devicetree/bindings/net/dsa/
Dbrcm,b53.yaml140 #size-cells = <0>;
148 #size-cells = <0>;
150 port@0 {
151 reg = <0>;
192 reg = <0x36000 0x1000>,
193 <0x3f308 0x8>,
194 <0x3f410 0xc>;
225 #size-cells = <0>;
227 port@0 {
229 reg = <0>;
/Linux-v6.1/drivers/misc/habanalabs/include/gaudi/asic_reg/
Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/Linux-v6.1/drivers/net/wireless/ath/ath10k/
Dcoredump.c18 {0x800, 0x810},
19 {0x820, 0x82C},
20 {0x830, 0x8F4},
21 {0x90C, 0x91C},
22 {0xA14, 0xA18},
23 {0xA84, 0xA94},
24 {0xAA8, 0xAD4},
25 {0xADC, 0xB40},
26 {0x1000, 0x10A4},
27 {0x10BC, 0x111C},
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_interrupts.c20 #define MDP_SSPP_TOP0_OFF 0x0
21 #define MDP_INTF_0_OFF 0x6A000
22 #define MDP_INTF_1_OFF 0x6A800
23 #define MDP_INTF_2_OFF 0x6B000
24 #define MDP_INTF_3_OFF 0x6B800
25 #define MDP_INTF_4_OFF 0x6C000
26 #define MDP_INTF_5_OFF 0x6C800
27 #define MDP_AD4_0_OFF 0x7C000
28 #define MDP_AD4_1_OFF 0x7D000
29 #define MDP_AD4_INTR_EN_OFF 0x41c
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
/Linux-v6.1/sound/soc/mediatek/mt8186/
Dmt8186-dai-i2s.c17 I2S_FMT_EIAJ = 0,
22 I2S_WLEN_16_BIT = 0,
27 I2S_HD_NORMAL = 0,
32 I2S1_SEL_O28_O29 = 0,
37 I2S_IN_PAD_CONNSYS = 0,
79 if (strncmp(name, "I2S0", 4) == 0) in get_i2s_id_by_name()
81 else if (strncmp(name, "I2S1", 4) == 0) in get_i2s_id_by_name()
83 else if (strncmp(name, "I2S2", 4) == 0) in get_i2s_id_by_name()
85 else if (strncmp(name, "I2S3", 4) == 0) in get_i2s_id_by_name()
97 if (dai_id < 0) in get_i2s_priv_by_name()
[all …]
/Linux-v6.1/arch/arm64/boot/dts/amlogic/
Dmeson-g12-common.dtsi106 reg = <0x0 0x05000000 0x0 0x300000>;
112 reg = <0x0 0x05300000 0x0 0x2000000>;
119 size = <0x0 0x10000000>;
120 alignment = <0x0 0x400000>;
137 reg = <0x0 0xfc000000 0x0 0x400000>,
138 <0x0 0xff648000 0x0 0x2000>,
139 <0x0 0xfc400000 0x0 0x200000>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
145 bus-range = <0x0 0xff>;
[all …]
/Linux-v6.1/drivers/clk/qcom/
Dgcc-msm8998.c29 { 250000000, 2000000000, 0 },
34 .offset = 0x0,
39 .enable_reg = 0x52000,
40 .enable_mask = BIT(0),
53 .offset = 0x0,
66 .offset = 0x0,
79 .offset = 0x0,
92 .offset = 0x0,
105 .offset = 0x1000,
110 .enable_reg = 0x52000,
[all …]
Dgcc-qcm2290.c46 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
75 { 0x1, 2 },
80 .offset = 0x0,
95 .offset = 0x1000,
98 .enable_reg = 0x79000,
113 .l = 0x3c,
114 .alpha = 0x0,
[all …]
Dgcc-sm8450.c39 .offset = 0x0,
42 .enable_reg = 0x62018,
43 .enable_mask = BIT(0),
56 { 0x1, 2 },
61 .offset = 0x0,
78 .offset = 0x4000,
81 .enable_reg = 0x62018,
95 .offset = 0x9000,
98 .enable_reg = 0x62018,
112 { P_BI_TCXO, 0 },
[all …]
Dgcc-sm8250.c36 .offset = 0x0,
39 .enable_reg = 0x52018,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 .offset = 0x76000,
78 .enable_reg = 0x52018,
92 .offset = 0x1c000,
95 .enable_reg = 0x52018,
109 { P_BI_TCXO, 0 },
[all …]
Dgcc-sm6375.c53 { 249600000, 2000000000, 0 },
57 { 595200000, 3600000000UL, 0 },
61 .offset = 0x0,
64 .enable_reg = 0x79000,
65 .enable_mask = BIT(0),
78 { 0x1, 2 },
83 .offset = 0x0,
100 { 0x3, 3 },
105 .offset = 0x0,
122 .offset = 0x1000,
[all …]
Dgcc-sdm845.c39 .offset = 0x0,
42 .enable_reg = 0x52000,
43 .enable_mask = BIT(0),
56 .offset = 0x76000,
59 .enable_reg = 0x52000,
73 .offset = 0x13000,
76 .enable_reg = 0x52000,
90 { 0x0, 1 },
91 { 0x1, 2 },
92 { 0x3, 4 },
[all …]
Dgcc-sm8150.c38 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x1a000,
84 .enable_reg = 0x52000,
[all …]
Dgcc-msm8996.c50 .offset = 0x00000,
53 .enable_reg = 0x52000,
54 .enable_mask = BIT(0),
80 .offset = 0x00000,
95 .enable_reg = 0x5200c,
96 .enable_mask = BIT(0),
112 .enable_reg = 0x5200c,
127 .offset = 0x77000,
130 .enable_reg = 0x52000,
144 .offset = 0x77000,
[all …]
Dgcc-sc8180x.c44 { 249600000, 2000000000, 0 },
48 .offset = 0x0,
53 .enable_reg = 0x52000,
54 .enable_mask = BIT(0),
67 { 0x0, 1 },
68 { 0x1, 2 },
69 { 0x3, 4 },
70 { 0x7, 8 },
75 .offset = 0x0,
90 .offset = 0x1000,
[all …]
/Linux-v6.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]

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