/Linux-v6.1/drivers/mfd/ |
D | si476x-prop.c | 25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array() 38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range() 49 0x0000, in si476x_core_is_valid_property_a10() 50 0x0500, 0x0501, in si476x_core_is_valid_property_a10() 51 0x0600, in si476x_core_is_valid_property_a10() 52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10() 53 0x0718, in si476x_core_is_valid_property_a10() 54 0x1207, 0x1208, in si476x_core_is_valid_property_a10() 55 0x2007, in si476x_core_is_valid_property_a10() 56 0x2300, in si476x_core_is_valid_property_a10() [all …]
|
/Linux-v6.1/drivers/staging/gdm724x/ |
D | hci.h | 7 #define LTE_GET_INFORMATION 0x3002 8 #define LTE_GET_INFORMATION_RESULT 0xB003 9 #define MAC_ADDRESS 0xA2 11 #define LTE_LINK_ON_OFF_INDICATION 0xB133 12 #define LTE_PDN_TABLE_IND 0xB143 14 #define LTE_TX_SDU 0x3200 15 #define LTE_RX_SDU 0xB201 16 #define LTE_TX_MULTI_SDU 0x3202 17 #define LTE_RX_MULTI_SDU 0xB203 19 #define LTE_DL_SDU_FLOW_CONTROL 0x3305 [all …]
|
/Linux-v6.1/drivers/net/ethernet/intel/ixgbevf/ |
D | regs.h | 7 #define IXGBE_VFCTRL 0x00000 8 #define IXGBE_VFSTATUS 0x00008 9 #define IXGBE_VFLINKS 0x00010 10 #define IXGBE_VFFRTIMER 0x00048 11 #define IXGBE_VFRXMEMWRAP 0x03190 12 #define IXGBE_VTEICR 0x00100 13 #define IXGBE_VTEICS 0x00104 14 #define IXGBE_VTEIMS 0x00108 15 #define IXGBE_VTEIMC 0x0010C 16 #define IXGBE_VTEIAC 0x00110 [all …]
|
/Linux-v6.1/drivers/gpu/drm/mediatek/ |
D | mtk_dp_reg.h | 9 #define SEC_OFFSET 0x4000 15 /* offset: 0x0 */ 16 #define DP_PHY_GLB_BIAS_GEN_00 0x0 18 #define DP_PHY_GLB_DPAUX_TX 0x8 20 #define MTK_DP_0034 0x34 36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0) 37 #define DP_PHY_LANE_TX_0 0x104 40 #define DP_PHY_LANE_TX_1 0x204 43 #define DP_PHY_LANE_TX_2 0x304 46 #define DP_PHY_LANE_TX_3 0x404 [all …]
|
/Linux-v6.1/Documentation/devicetree/bindings/phy/ |
D | qcom,msm8996-qmp-pcie-phy.yaml | 57 "^phy@[0-9a-f]+$": 92 const: 0 98 const: 0 130 reg = <0x34000 0x488>; 133 ranges = <0x0 0x34000 0x4000>; 149 reg = <0x1000 0x130>, 150 <0x1200 0x200>, 151 <0x1400 0x1dc>; 156 #clock-cells = <0>; 159 #phy-cells = <0>; [all …]
|
/Linux-v6.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
D | polaris10_smumgr.c | 55 #define POLARIS10_SMC_SIZE 0x20000 58 #define MC_CG_ARB_FREQ_F1 0x0b 63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, 65 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5… 83 …0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000… 84 …0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000… 85 …0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000… 86 …0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000… 87 …0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100… [all …]
|
/Linux-v6.1/arch/powerpc/boot/dts/fsl/ |
D | mpc8569si-post.dtsi | 39 interrupts = <19 2 0 0>; 40 sleep = <&pmc 0x08000000>; 43 /* controller at 0xa000 */ 49 bus-range = <0 255>; 51 interrupts = <26 2 0 0>; 52 sleep = <&pmc 0x20000000>; 54 pcie@0 { 55 reg = <0 0 0 0 0>; 60 interrupts = <26 2 0 0>; 61 interrupt-map-mask = <0xf800 0 0 7>; [all …]
|
/Linux-v6.1/drivers/net/ethernet/chelsio/cxgb/ |
D | espi.c | 47 #define TRICN_CMD_READ 0x11 48 #define TRICN_CMD_WRITE 0x21 62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write() 86 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init() 87 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init() 88 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init() 91 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init() 93 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init() 95 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init() 96 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init() [all …]
|
D | pm3393.c | 45 #define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \ 88 return 0; in pmread() 94 return 0; in pmwrite() 100 return 0; in pm3393_reset() 117 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable() 118 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable() 119 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable() 120 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable() 123 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_enable() 124 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_enable() [all …]
|
/Linux-v6.1/drivers/ata/ |
D | sata_vsc.c | 36 VSC_MMIO_BAR = 0, 39 VSC_SATA_INT_STAT_OFFSET = 0x00, 40 VSC_SATA_INT_MASK_OFFSET = 0x04, 43 VSC_SATA_TF_CMD_OFFSET = 0x00, 44 VSC_SATA_TF_DATA_OFFSET = 0x00, 45 VSC_SATA_TF_ERROR_OFFSET = 0x04, 46 VSC_SATA_TF_FEATURE_OFFSET = 0x06, 47 VSC_SATA_TF_NSECT_OFFSET = 0x08, 48 VSC_SATA_TF_LBAL_OFFSET = 0x0c, 49 VSC_SATA_TF_LBAM_OFFSET = 0x10, [all …]
|
D | pata_icside.c | 16 #define ICS_IDENT_OFFSET 0x2280 18 #define ICS_ARCIN_V5_INTRSTAT 0x0000 19 #define ICS_ARCIN_V5_INTROFFSET 0x0004 21 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200 22 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290 23 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 24 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290 33 .dataoffset = 0x2800, 34 .ctrloffset = 0x2b80, 39 .dataoffset = 0x2000, [all …]
|
/Linux-v6.1/arch/powerpc/boot/dts/ |
D | mpc836x_rdk.dts | 32 #size-cells = <0>; 34 PowerPC,8360@0 { 36 reg = <0>; 42 timebase-frequency = <0>; 43 bus-frequency = <0>; 44 clock-frequency = <0>; 51 reg = <0 0>; 60 ranges = <0 0xe0000000 0x200000>; 61 reg = <0xe0000000 0x200>; 63 bus-frequency = <0>; [all …]
|
D | mpc832x_mds.dts | 39 #size-cells = <0>; 41 PowerPC,8323@0 { 43 reg = <0x0>; 48 timebase-frequency = <0>; 49 bus-frequency = <0>; 50 clock-frequency = <0>; 56 reg = <0x00000000 0x08000000>; 61 reg = <0xf8000000 0x8000>; 69 ranges = <0x0 0xe0000000 0x00100000>; 70 reg = <0xe0000000 0x00000200>; [all …]
|
D | kmeter1.dts | 29 #size-cells = <0>; 31 PowerPC,8360@0 { 33 reg = <0x0>; 38 timebase-frequency = <0>; /* Filled in by U-Boot */ 39 bus-frequency = <0>; /* Filled in by U-Boot */ 40 clock-frequency = <0>; /* Filled in by U-Boot */ 46 reg = <0 0>; /* Filled in by U-Boot */ 54 ranges = <0x0 0xe0000000 0x00200000>; 55 reg = <0xe0000000 0x00000200>; 56 bus-frequency = <0>; /* Filled in by U-Boot */ [all …]
|
/Linux-v6.1/sound/soc/codecs/ |
D | rt711-sdca-sdw.c | 22 case 0x201a ... 0x2027: in rt711_sdca_readable_register() 23 case 0x2029 ... 0x202a: in rt711_sdca_readable_register() 24 case 0x202d ... 0x2034: in rt711_sdca_readable_register() 25 case 0x2200 ... 0x2204: in rt711_sdca_readable_register() 26 case 0x2206 ... 0x2212: in rt711_sdca_readable_register() 27 case 0x2220 ... 0x2223: in rt711_sdca_readable_register() 28 case 0x2230 ... 0x2239: in rt711_sdca_readable_register() 29 case 0x2f01 ... 0x2f0f: in rt711_sdca_readable_register() 30 case 0x2f30 ... 0x2f36: in rt711_sdca_readable_register() 31 case 0x2f50 ... 0x2f5a: in rt711_sdca_readable_register() [all …]
|
/Linux-v6.1/arch/powerpc/kernel/ |
D | head_85xx.S | 70 li r25,0 /* phys kernel start (low) */ 71 li r24,0 /* CPU number */ 72 li r23,0 /* phys kernel start (high) */ 83 0: mflr r8 84 addis r3,r8,(is_second_reloc - 0b)@ha 85 lwz r19,(is_second_reloc - 0b)@l(r3) 102 addis r4,r8,(kernstart_addr - 0b)@ha 103 addi r4,r4,(kernstart_addr - 0b)@l 106 addis r6,r8,(memstart_addr - 0b)@ha 107 addi r6,r6,(memstart_addr - 0b)@l [all …]
|
D | kgdb.c | 38 { 0x0100, 0x02 /* SIGINT */ }, /* system reset */ 39 { 0x0200, 0x0b /* SIGSEGV */ }, /* machine check */ 40 { 0x0300, 0x0b /* SIGSEGV */ }, /* data access */ 41 { 0x0400, 0x0b /* SIGSEGV */ }, /* instruction access */ 42 { 0x0500, 0x02 /* SIGINT */ }, /* external interrupt */ 43 { 0x0600, 0x0a /* SIGBUS */ }, /* alignment */ 44 { 0x0700, 0x05 /* SIGTRAP */ }, /* program check */ 45 { 0x0800, 0x08 /* SIGFPE */ }, /* fp unavailable */ 46 { 0x0900, 0x0e /* SIGALRM */ }, /* decrementer */ 47 { 0x0c00, 0x14 /* SIGCHLD */ }, /* system call */ [all …]
|
/Linux-v6.1/drivers/net/ethernet/amd/ |
D | ariadne.h | 17 * Publication #16907, Rev. B, Amendment/0, May 1994 62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */ 63 #define CSR1 0x0100 /* - IADR[15:0] */ 64 #define CSR2 0x0200 /* - IADR[23:16] */ 65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */ 66 #define CSR4 0x0400 /* - Test and Features Control */ 67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */ 68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */ 69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */ 70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */ [all …]
|
/Linux-v6.1/drivers/gpu/drm/meson/ |
D | meson_viu.c | 46 VIU_MATRIX_OSD_EOTF = 0, 51 VIU_LUT_OSD_EOTF = 0, 63 0, 0, 0, /* pre offset */ 67 0, 0, 0, /* 10'/11'/12' */ 68 0, 0, 0, /* 20'/21'/22' */ 70 0, 0, 0 /* mode, right_shift, clip_en */ 85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix() 87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix() 89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix() 91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix() [all …]
|
/Linux-v6.1/drivers/media/usb/pwc/ |
D | pwc-ctrl.c | 41 #define GET_STATUS_B00 0x0B00 42 #define SENSOR_TYPE_FORMATTER1 0x0C00 43 #define GET_STATUS_3000 0x3000 44 #define READ_RAW_Y_MEAN_FORMATTER 0x3100 45 #define SET_POWER_SAVE_MODE_FORMATTER 0x3200 46 #define MIRROR_IMAGE_FORMATTER 0x3300 47 #define LED_FORMATTER 0x3400 48 #define LOWLIGHT 0x3500 49 #define GET_STATUS_3600 0x3600 50 #define SENSOR_TYPE_FORMATTER2 0x3700 [all …]
|
/Linux-v6.1/drivers/pinctrl/mediatek/ |
D | pinctrl-mt7629.c | 12 MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1) 15 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4), 19 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1), 23 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1), 27 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1), 31 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1), 32 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1), 33 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1), 34 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1), 35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1), [all …]
|
/Linux-v6.1/drivers/mailbox/ |
D | mtk-cmdq-mailbox.c | 20 #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) 24 #define CMDQ_CURR_IRQ_STATUS 0x10 25 #define CMDQ_SYNC_TOKEN_UPDATE 0x68 26 #define CMDQ_THR_SLOT_CYCLES 0x30 27 #define CMDQ_THR_BASE 0x100 28 #define CMDQ_THR_SIZE 0x80 29 #define CMDQ_THR_WARM_RESET 0x00 30 #define CMDQ_THR_ENABLE_TASK 0x04 31 #define CMDQ_THR_SUSPEND_TASK 0x08 32 #define CMDQ_THR_CURR_STATUS 0x0c [all …]
|
/Linux-v6.1/drivers/soc/fsl/qbman/ |
D | bman.c | 40 #define BM_REG_RCR_PI_CINH 0x3000 41 #define BM_REG_RCR_CI_CINH 0x3100 42 #define BM_REG_RCR_ITR 0x3200 43 #define BM_REG_CFG 0x3300 44 #define BM_REG_SCN(n) (0x3400 + ((n) << 6)) 45 #define BM_REG_ISR 0x3e00 46 #define BM_REG_IER 0x3e40 47 #define BM_REG_ISDR 0x3e80 48 #define BM_REG_IIR 0x3ec0 51 #define BM_CL_CR 0x0000 [all …]
|
/Linux-v6.1/drivers/media/tuners/ |
D | xc4000.c | 29 MODULE_PARM_DESC(debug, "Debugging level (0 to 2, default: 0 (off))."); 33 MODULE_PARM_DESC(no_poweroff, "Power management (1: disabled, 2: enabled, 0 (default): use device-s… 46 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0); 107 #define XC_POWERED_DOWN 0x80000000U 110 #define XC_RF_MODE_AIR 0 114 #define XC_PRODUCT_ID_FW_NOT_LOADED 0x2000 115 #define XC_PRODUCT_ID_XC4000 0x0FA0 116 #define XC_PRODUCT_ID_XC4100 0x1004 119 #define XREG_INIT 0x00 120 #define XREG_VIDEO_MODE 0x01 [all …]
|
/Linux-v6.1/drivers/gpu/drm/bridge/synopsys/ |
D | dw-hdmi.h | 10 #define HDMI_DESIGN_ID 0x0000 11 #define HDMI_REVISION_ID 0x0001 12 #define HDMI_PRODUCT_ID0 0x0002 13 #define HDMI_PRODUCT_ID1 0x0003 14 #define HDMI_CONFIG0_ID 0x0004 15 #define HDMI_CONFIG1_ID 0x0005 16 #define HDMI_CONFIG2_ID 0x0006 17 #define HDMI_CONFIG3_ID 0x0007 20 #define HDMI_IH_FC_STAT0 0x0100 21 #define HDMI_IH_FC_STAT1 0x0101 [all …]
|