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/Linux-v5.15/drivers/video/fbdev/
Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/Linux-v5.15/drivers/clk/mediatek/
Dclk-mt8192.c709 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0,
712 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1,
715 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2),
717 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3,
721 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),
723 mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5),
725 img1_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
727 img2_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
730 ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8),
732 dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9),
[all …]
Dclk-mt6779.c640 0x20, 0x24, 0x28, 0, 2, 7,
641 0x004, 0, CLK_IS_CRITICAL),
643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
[all …]
Dclk-mt8183.c21 #define INFRA_RST0_SET_OFFSET 0x120
526 axi_parents, 0x40,
527 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
529 mm_parents, 0x40,
530 0x44, 0x48, 8, 3, 15, 0x004, 1),
532 img_parents, 0x40,
533 0x44, 0x48, 16, 3, 23, 0x004, 2),
535 cam_parents, 0x40,
536 0x44, 0x48, 24, 4, 31, 0x004, 3),
539 dsp_parents, 0x50,
[all …]
/Linux-v5.15/include/dt-bindings/clock/
Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
14 #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
15 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
16 #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
17 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
18 #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
19 #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
20 #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
21 #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
22 #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
[all …]
/Linux-v5.15/arch/sh/include/mach-common/mach/
Dlboxre2.h12 #define IRQ_CF1 evt2irq(0x320) /* CF1 */
13 #define IRQ_CF0 evt2irq(0x340) /* CF0 */
14 #define IRQ_INTD evt2irq(0x360) /* INTD */
15 #define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
16 #define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
17 #define IRQ_INTA evt2irq(0x3c0) /* INTA */
/Linux-v5.15/drivers/memory/tegra/
Dtegra210-mc.h12 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
13 #define MC_LATENCY_ALLOWANCE_HC_0 0x310
14 #define MC_LATENCY_ALLOWANCE_HC_1 0x314
15 #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
16 #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
17 #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
18 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
19 #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
20 #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
21 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Drockchip-usb-phy.yaml7 title: Rockchip USB2.0 phy
26 const: 0
36 "usb-phy@[0-9a-f]+$":
44 const: 0
53 const: 0
75 #size-cells = <0>;
78 reg = <0x320>;
79 #phy-cells = <0>;
/Linux-v5.15/Documentation/devicetree/bindings/display/panel/
Dsamsung,amoled-mipi-dsi.yaml29 # Samsung S6E63J0X03 1.63" 320x320 AMOLED panel
62 #size-cells = <0>;
64 panel@0 {
66 reg = <0>;
69 reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgp104.c29 .bundle_size = 0x3000,
30 .bundle_min_gpm_fifo_depth = 0x180,
31 .bundle_token_limit = 0x900,
33 .pagepool_size = 0x20000,
35 .attrib_nr_max = 0x4b0,
36 .attrib_nr = 0x320,
37 .alpha_nr_max = 0xc00,
38 .alpha_nr = 0x800,
39 .gfxp_nr = 0xba8,
/Linux-v5.15/arch/sh/boards/
Dboard-edosk7705.c21 #define SMC_IOBASE 0xA2000000
22 #define SMC_IO_OFFSET 0x300
25 #define ETHERNET_IRQ evt2irq(0x320)
38 [0] = {
/Linux-v5.15/arch/sh/include/mach-landisk/mach/
Diodata_landisk.h16 #define PA_USB 0xa4000000 /* USB Controller M66590 */
18 #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
19 #define PA_LED 0xb0000001 /* LED Control Register */
20 #define PA_STATUS 0xb0000002 /* Switch Status Register */
21 #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
22 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
23 #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
25 #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
27 #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
28 #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
[all …]
/Linux-v5.15/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/Linux-v5.15/drivers/scsi/cxlflash/
Dmain.h25 #define PCI_DEVICE_ID_IBM_CORSA 0x04F0
26 #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600
27 #define PCI_DEVICE_ID_IBM_BRIARD 0x0624
29 /* Since there is only one target, make it 0 */
30 #define CXLFLASH_TARGET 0
40 #define FC_MTIP_CMDCONFIG 0x010
41 #define FC_MTIP_STATUS 0x018
42 #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */
43 #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */
44 #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */
[all …]
/Linux-v5.15/sound/isa/
Dcmi8328.c35 static const int cmi8328_ports[] = { 0x530, 0xe80, 0xf40, 0x604 };
38 static int index[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = -1};
39 static char *id[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = NULL};
40 static long port[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_PORT};
41 static int irq[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_IRQ};
42 static int dma1[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_DMA};
43 static int dma2[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_DMA};
44 static long mpuport[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_PORT};
45 static int mpuirq[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_IRQ};
47 static bool gameport[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = true};
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/Linux-v5.15/drivers/pinctrl/mediatek/
Dpinctrl-mt7622.c15 PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
16 PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
17 PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
18 PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
19 PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
20 PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
21 PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
22 PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
23 PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
24 PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
[all …]
/Linux-v5.15/drivers/net/wireless/intersil/p54/
Dp54usb.h19 #define NET2280_BASE 0x10000000
20 #define NET2280_BASE2 0x20000000
30 #define NET2280_CLK_STOP (0 << LOCAL_CLOCK_FREQUENCY)
44 #define NET2280_DEVINIT 0x00
45 #define NET2280_USBIRQENB1 0x24
46 #define NET2280_IRQSTAT1 0x2c
47 #define NET2280_FIFOCTL 0x38
48 #define NET2280_GPIOCTL 0x50
49 #define NET2280_RELNUM 0x88
50 #define NET2280_EPA_RSP 0x324
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/display/include/
Ddpcd_defs.h31 #define DP_SINK_HW_REVISION_START 0x409
35 DPCD_REV_10 = 0x10,
36 DPCD_REV_11 = 0x11,
37 DPCD_REV_12 = 0x12,
38 DPCD_REV_13 = 0x13,
39 DPCD_REV_14 = 0x14
44 DOWNSTREAM_DP = 0,
51 LINK_TEST_PATTERN_NONE = 0,
58 TEST_COLOR_FORMAT_RGB = 0,
64 TEST_BIT_DEPTH_6 = 0,
[all …]
/Linux-v5.15/drivers/staging/rtl8192u/
Dr8192U_hw.h23 #define RTL8187_REQT_READ 0xc0
24 #define RTL8187_REQT_WRITE 0x40
25 #define RTL8187_REQ_GET_REGS 0x05
26 #define RTL8187_REQ_SET_REGS 0x05
35 #define RTL8190_EEPROM_ID 0x8129
36 #define EEPROM_VID 0x02
37 #define EEPROM_PID 0x04
38 #define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
40 #define EEPROM_TX_POWER_DIFF 0x1F
41 #define EEPROM_THERMAL_METER 0x20
[all …]
/Linux-v5.15/drivers/misc/habanalabs/include/goya/asic_reg/
Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/Linux-v5.15/drivers/net/ethernet/mediatek/
Dmtk_ppe_regs.h7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
39 #define MTK_PPE_IP_PROTO_CHK 0x208
40 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
43 #define MTK_PPE_TB_CFG 0x21c
44 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
76 #define MTK_PPE_TB_BASE 0x220
78 #define MTK_PPE_TB_USED 0x224
79 #define MTK_PPE_TB_USED_NUM GENMASK(13, 0)
[all …]
/Linux-v5.15/include/soc/at91/
Dsama7-ddr.h17 #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
22 #define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
24 #define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */
28 #define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
29 #define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
31 #define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
32 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
33 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
36 #define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */
39 #define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */
[all …]
/Linux-v5.15/drivers/staging/media/atomisp/pci/
Datomisp-regs.h23 #define PCICMDSTS 0x01
24 #define INTR 0x0f
25 #define MSI_CAPID 0x24
26 #define MSI_ADDRESS 0x25
27 #define MSI_DATA 0x26
28 #define INTR_CTL 0x27
30 #define PCI_MSI_CAPID 0x90
31 #define PCI_MSI_ADDR 0x94
32 #define PCI_MSI_DATA 0x98
33 #define PCI_INTERRUPT_CTRL 0x9C
[all …]

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