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/Linux-v5.15/drivers/net/wireless/quantenna/qtnfmac/pcie/
Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0)
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4)
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310)
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319)
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c)
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324)
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
Dbus.json4 "EventCode": "0x314",
10 "EventCode": "0x315",
16 "EventCode": "0x316",
22 "EventCode": "0x318",
28 "EventCode": "0x319",
34 "EventCode": "0x31A",
40 "EventCode": "0x31B",
46 "EventCode": "0x31C",
52 "EventCode": "0x31D",
58 "EventCode": "0x31E",
/Linux-v5.15/arch/arm/boot/dts/
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/Linux-v5.15/drivers/media/common/b2c2/
Dflexcop-reg.h11 FLEXCOP_UNK = 0,
18 FC_UNK = 0,
32 FC_USB = 0,
47 #define fc_data_Tag_ID_DVB 0x3e
48 #define fc_data_Tag_ID_ATSC 0x3f
49 #define fc_data_Tag_ID_IDSB 0x8b
51 #define fc_key_code_default 0x1
52 #define fc_key_code_even 0x2
53 #define fc_key_code_odd 0x3
64 FC_WRITE = 0,
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml58 cpu 2, reg + 0x4;
59 cpu 3, reg + 0x8;
99 ranges = <0 0x802000 0x1000>;
100 reg = <0x802000 0x1000>;
102 smp-offset = <0x31c>;
103 resume-offset = <0x308>;
104 reboot-offset = <0x4>;
106 clock: clock@0 {
108 reg = <0 0x10000>;
116 reg = <0x10000000 0x1000>;
[all …]
/Linux-v5.15/tools/perf/arch/powerpc/util/
Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/Linux-v5.15/drivers/clk/meson/
Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
Dgxbb.h17 #define SCR 0x2C /* 0x0b offset in data sheet */
18 #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
20 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
21 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
22 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
23 #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
24 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
25 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
27 #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
28 #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
[all …]
/Linux-v5.15/drivers/video/fbdev/
Dwm8505fb.c50 for (i = 0; i < 0x200; i += 4) in wm8505fb_init_hw()
51 writel(0, fbi->regbase + i); in wm8505fb_init_hw()
59 * 0x31C sets the correct color mode (RGB565) for WM8650 in wm8505fb_init_hw()
60 * Bit 8+9 (0x300) are ignored on WM8505 as reserved in wm8505fb_init_hw()
62 writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE); in wm8505fb_init_hw()
70 writel(0xf, fbi->regbase + WMT_GOVR_FHI); in wm8505fb_init_hw()
75 return 0; in wm8505fb_init_hw()
92 writel(0, fbi->regbase + WMT_GOVR_TG); in wm8505fb_set_timing()
106 return 0; in wm8505fb_set_timing()
120 info->var.red.msb_right = 0; in wm8505fb_set_par()
[all …]
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgk104.c36 nvkm_wr32(device, 0x00c800, 0x00000000); in magic_()
37 nvkm_wr32(device, 0x00c808, 0x00000000); in magic_()
38 nvkm_wr32(device, 0x00c800, ctrl); in magic_()
40 if (nvkm_rd32(device, 0x00c800) & 0x40000000) { in magic_()
42 nvkm_wr32(device, 0x00c804, 0x00000000); in magic_()
46 nvkm_wr32(device, 0x00c800, 0x00000000); in magic_()
52 magic_(device, 0x8000a41f | ctrl, 6); in magic()
53 magic_(device, 0x80000421 | ctrl, 1); in magic()
61 if (!(nvkm_fuse_read(device->fuse, 0x31c) & 0x00000001)) in gk104_pmu_pgob()
64 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gk104_pmu_pgob()
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/Linux-v5.15/drivers/media/pci/tw68/
Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
[all …]
/Linux-v5.15/drivers/media/platform/
Dvia-camera.h5 #define VCR_INTCTRL 0x300 /* Capture interrupt control */
6 #define VCR_IC_EAV 0x0001 /* End of active video status */
7 #define VCR_IC_EVBI 0x0002 /* End of VBI status */
8 #define VCR_IC_FBOTFLD 0x0004 /* "flipping" Bottom field is active */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
10 #define VCR_IC_VSYNC 0x0020 /* 0 = VB, 1 = active video */
11 #define VCR_IC_BOTFLD 0x0040 /* Bottom field is active */
12 #define VCR_IC_FFULL 0x0080 /* FIFO full */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
[all …]
/Linux-v5.15/arch/arm/mach-s5pv210/
Dregs-clock.h12 #define S3C_ADDR_BASE 0xF6000000
14 #define S3C_VA_SYS S3C_ADDR(0x00100000)
18 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
19 #define S5P_MPLL_LOCK S5P_CLKREG(0x08)
20 #define S5P_EPLL_LOCK S5P_CLKREG(0x10)
21 #define S5P_VPLL_LOCK S5P_CLKREG(0x20)
23 #define S5P_APLL_CON S5P_CLKREG(0x100)
24 #define S5P_MPLL_CON S5P_CLKREG(0x108)
25 #define S5P_EPLL_CON S5P_CLKREG(0x110)
26 #define S5P_EPLL_CON1 S5P_CLKREG(0x114)
[all …]
/Linux-v5.15/drivers/net/ethernet/
Ddnet.h19 #define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */
20 #define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */
21 #define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */
22 #define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */
25 #define DNET_VERCAPS 0x100 /* VERCAPS */
26 #define DNET_INTR_SRC 0x104 /* INTR_SRC */
27 #define DNET_INTR_ENB 0x108 /* INTR_ENB */
28 #define DNET_RX_STATUS 0x10C /* RX_STATUS */
29 #define DNET_TX_STATUS 0x110 /* TX_STATUS */
30 #define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */
[all …]
/Linux-v5.15/arch/powerpc/include/asm/
Dpasemi_dma.h13 /* status register layout in IOB region, at 0xfb800000 */
24 PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */
25 PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */
26 PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */
27 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
28 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
29 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
30 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
31 PAS_DMA_COM_CFG = 0x114, /* Common config reg */
32 PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */
[all …]
/Linux-v5.15/drivers/crypto/qce/
Dregs-v5.h11 #define REG_VERSION 0x000
12 #define REG_STATUS 0x100
13 #define REG_STATUS2 0x104
14 #define REG_ENGINES_AVAIL 0x108
15 #define REG_FIFO_SIZES 0x10c
16 #define REG_SEG_SIZE 0x110
17 #define REG_GOPROC 0x120
18 #define REG_ENCR_SEG_CFG 0x200
19 #define REG_ENCR_SEG_SIZE 0x204
20 #define REG_ENCR_SEG_START 0x208
[all …]
/Linux-v5.15/drivers/phy/st/
Dphy-spear1340-miphy.c22 #define SPEAR1340_PCM_CFG 0x100
24 #define SPEAR1340_PCM_WKUP_CFG 0x104
25 #define SPEAR1340_SWITCH_CTR 0x108
27 #define SPEAR1340_PERIP1_SW_RST 0x318
29 #define SPEAR1340_PERIP2_SW_RST 0x31C
30 #define SPEAR1340_PERIP3_SW_RST 0x320
33 #define SPEAR1340_PCIE_SATA_CFG 0x424
43 #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
45 #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
57 #define SPEAR1340_PCIE_MIPHY_CFG 0x428
[all …]
/Linux-v5.15/drivers/usb/isp1760/
Disp1760-regs.h24 #define ISP176x_HC_VERSION 0x002
25 #define ISP176x_HC_HCSPARAMS 0x004
26 #define ISP176x_HC_HCCPARAMS 0x008
29 #define ISP176x_HC_USBCMD 0x020
30 #define ISP176x_HC_USBSTS 0x024
31 #define ISP176x_HC_FRINDEX 0x02c
33 #define ISP176x_HC_CONFIGFLAG 0x060
34 #define ISP176x_HC_PORTSC1 0x064
36 #define ISP176x_HC_ISO_PTD_DONEMAP 0x130
37 #define ISP176x_HC_ISO_PTD_SKIPMAP 0x134
[all …]
/Linux-v5.15/drivers/platform/x86/intel/pmc/
Dcore.h17 #define PMC_BASE_ADDR_DEFAULT 0xFE000000
20 #define SPT_PMC_PCI_DEVICE_ID 0x9d21
21 #define SPT_PMC_BASE_ADDR_OFFSET 0x48
22 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
23 #define SPT_PMC_PM_CFG_OFFSET 0x18
24 #define SPT_PMC_PM_STS_OFFSET 0x1c
25 #define SPT_PMC_MTPMC_OFFSET 0x20
26 #define SPT_PMC_MFPMC_OFFSET 0x38
27 #define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
28 #define SPT_PMC_VRIC1_OFFSET 0x31c
[all …]
/Linux-v5.15/drivers/gpu/drm/sun4i/
Dsun4i_tcon.h19 #define SUN4I_TCON_GCTL_REG 0x0
21 #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
22 #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
23 #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
25 #define SUN4I_TCON_GINT0_REG 0x4
33 #define SUN4I_TCON_GINT1_REG 0x8
35 #define SUN4I_TCON_FRM_CTL_REG 0x10
41 #define SUN4I_TCON0_FRM_SEED_PR_REG 0x14
42 #define SUN4I_TCON0_FRM_SEED_PG_REG 0x18
43 #define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c
[all …]
/Linux-v5.15/Documentation/admin-guide/
Dpstore-blk.rst59 with no leading 0x, for example b302.
97 */sys/fs/pstore/pmsg-pstore-blk-0*.
108 available in */sys/fs/pstore/console-pstore-blk-0*.
121 combined and available in */sys/fs/pstore/ftrace-pstore-blk-0*.
132 # tail /sys/fs/pstore/ftrace-pstore-blk-0
133 CPU:0 ts:5914676 c0063828 c0063b94 call_cpuidle <- cpu_startup_entry+0x1b8/0x1e0
134 CPU:0 ts:5914678 c039ecdc c006385c cpuidle_enter_state <- call_cpuidle+0x44/0x48
135 CPU:0 ts:5914680 c039e9a0 c039ecf0 cpuidle_enter_freeze <- cpuidle_enter_state+0x304/0x314
136 CPU:0 ts:5914681 c0063870 c039ea30 sched_idle_set_state <- cpuidle_enter_state+0x44/0x314
137 CPU:1 ts:5916720 c0160f59 c015ee04 kernfs_unmap_bin_file <- __kernfs_remove+0x140/0x204
[all …]

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