Searched +full:0 +full:x2d000000 (Results 1 – 11 of 11) sorted by relevance
/Linux-v5.10/arch/arm/boot/dts/ |
D | omap3-sbc-t3730.dts | 21 pinctrl-0 = <&sb_t35_usb_hub_pins>; 25 OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ 31 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ 32 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ 33 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
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D | omap3-sbc-t3530.dts | 21 pinctrl-0 = <&sb_t35_usb_hub_pins>; 25 OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ 31 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ 32 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ 33 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ 37 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
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D | omap3-sbc-t3517.dts | 34 pinctrl-0 = < 41 OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ 42 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ 48 OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ 55 pinctrl-0 = < 74 ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ 75 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
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D | omap3-sb-t35.dtsi | 13 pinctrl-0 = <&tfp410_pins>; 17 #size-cells = <0>; 19 port@0 { 20 reg = <0>; 52 pinctrl-0 = <&sb_t35_audio_amp>; 61 OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ 62 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ 68 OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ 74 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ 75 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/ |
D | arm,gic-v3.yaml | 33 enum: [ 0, 1, 2 ] 46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 51 SPI interrupts are in the range [0-987]. PPI interrupts are in the 52 range [0-15]. Extented SPI interrupts are in the range [0-1023]. 53 Extended PPI interrupts are in the range [0-127]. 56 bits[3:0] trigger type and level flags. 68 of 0 if present. 95 multipleOf: 0x10000 96 exclusiveMinimum: 0 136 "^interrupt-partition-[0-9]+$": [all …]
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/Linux-v5.10/arch/arm64/boot/dts/arm/ |
D | juno-base.dtsi | 12 reg = <0x0 0x2a810000 0x0 0x10000>; 16 ranges = <0 0x0 0x2a820000 0x20000>; 21 reg = <0x10000 0x10000>; 27 reg = <0x0 0x2b1f0000 0x0 0x1000>; 39 reg = <0x0 0x2b400000 0x0 0x10000>; 51 reg = <0x0 0x2b500000 0x0 0x10000>; 62 reg = <0x0 0x2b600000 0x0 0x10000>; 68 power-domains = <&scpi_devpd 0>; 73 reg = <0x0 0x2c010000 0 0x1000>, 74 <0x0 0x2c02f000 0 0x2000>, [all …]
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/Linux-v5.10/arch/hexagon/kernel/ |
D | vm_init_segtable.S | 16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages. 46 /* VA 0x00000000 */ 59 /* VA 0x40000000 */ 68 /* VA 0x80000000 */ 74 /*0xa8*/.word X,X,X,X 77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000) 79 /*0xa9*/.word X,X,X,X 81 /*0xaa*/.word X,X,X,X 82 /*0xab*/.word X,X,X,X 83 /*0xac*/.word X,X,X,X [all …]
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/Linux-v5.10/crypto/ |
D | aes_generic.c | 67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6, 68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591, 69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56, 70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec, 71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa, 72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb, 73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45, 74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b, 75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c, 76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83, [all …]
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/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
D | nbio_7_0_default.h | 26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000 27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000 28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000 29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000 30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000 31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000 32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000 33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000 34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000 35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000 [all …]
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D | nbio_2_3_default.h | 26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000 27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000 28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000 32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 34 #define mmPCIE_INDEX_DEFAULT 0x00000000 35 #define mmPCIE_DATA_DEFAULT 0x00000000 36 #define mmPCIE_INDEX2_DEFAULT 0x00000000 37 #define mmPCIE_DATA2_DEFAULT 0x00000000 38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 [all …]
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D | nbio_6_1_default.h | 26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000 27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000 28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000 29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000 30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000 31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000 32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000 33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000 34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000 35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000 [all …]
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