Home
last modified time | relevance | path

Searched +full:0 +full:x28000000 (Results 1 – 25 of 65) sorted by relevance

123

/Linux-v6.1/arch/arm/mach-s3c/
Dmap-s3c64xx.h22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
Dmap-s3c24xx.h19 #define S3C2410_PA_IRQ (0x4A000000)
23 #define S3C2410_PA_MEMCTRL (0x48000000)
27 #define S3C2410_PA_TIMER (0x51000000)
34 #define S3C2410_PA_USBDEV (0x52000000)
38 #define S3C2410_PA_WATCHDOG (0x53000000)
52 #define S3C2410_PA_USBHOST (0x49000000)
55 #define S3C2416_PA_HSUDC (0x49800000)
59 #define S3C2410_PA_DMA (0x4B000000)
63 #define S3C2410_PA_CLKPWR (0x4C000000)
66 #define S3C2410_PA_LCD (0x4D000000)
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Den7523.dtsi20 reg = <0x84000000 0xA00000>;
25 reg = <0x84B00000 0x100000>;
30 reg = <0x85000000 0x1A00000>;
35 reg = <0x86B00000 0x100000>;
40 reg = <0x86D00000 0x100000>;
51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0x0>;
76 reg = <0x1>;
89 reg = <0x1fa20000 0x400>,
[all …]
Dlpc4337-ciaa.dts35 reg = <0x28000000 0x0800000>; /* 8 MB */
173 pinctrl-0 = <&i2c0_pins>;
178 reg = <0x50>;
183 reg = <0x51>;
188 reg = <0x54>;
196 pinctrl-0 = <&enet_rmii_pins>;
206 pinctrl-0 = <&ssp_pins>;
214 pinctrl-0 = <&uart2_pins>;
220 pinctrl-0 = <&uart3_pins>;
Domap3430-sdp.dts15 reg = <0x80000000 0x10000000>; /* 256 MB */
23 reg = <0x48>;
50 ranges = <0 0 0x10000000 0x08000000>,
51 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
52 <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */
54 nor@0,0 {
59 reg = <0 0 0x08000000>;
63 gpmc,cs-on-ns = <0>;
84 partition@0 {
86 reg = <0 0x40000>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dqcom,lcc.txt19 reg = <0x28000000 0x1000>;
/Linux-v6.1/arch/sh/boards/mach-rsk/
Ddevices-rsk7264.c24 [0] = {
25 .start = 0x28000000,
26 .end = 0x280000ff,
/Linux-v6.1/arch/arm64/boot/dts/renesas/
Dr9a09g011-v2mevk2.dts31 reg = <0x0 0x58000000 0x0 0x28000000>;
36 reg = <0x1 0x80000000 0x0 0x80000000>;
46 phy0: ethernet-phy@0 {
49 reg = <0>;
58 pinctrl-0 = <&i2c0_pins>;
65 pinctrl-0 = <&i2c2_pins>;
73 pinmux = <RZV2M_PORT_PINMUX(5, 0, 2)>, /* SDA */
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dtoshiba,visconti-dwmac.yaml64 reg = <0 0x28000000 0 0x10000>;
76 #address-cells = <0x1>;
77 #size-cells = <0x0>;
82 reg = <0x1>;
/Linux-v6.1/arch/sparc/include/asm/
Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/arm/
Darm,coresight-stm.yaml90 reg = <0x20100000 0x1000>,
91 <0x28000000 0x180000>;
/Linux-v6.1/arch/arm/mach-pxa/
Dpalmtx.h71 #define PALMTX_PCMCIA_PHYS 0x28000000
72 #define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000)
73 #define PALMTX_PCMCIA_SIZE 0x100000
75 #define PALMTX_PHYS_RAM_START 0xa0000000
76 #define PALMTX_PHYS_IO_START 0x40000000
78 #define PALMTX_STR_BASE 0xa0200000
80 #define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
85 #define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000)
86 #define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000)
95 #define PALMTX_BAT_MAX_CURRENT 0 /* unknown */
[all …]
Dpcm990_baseboard.h29 #define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
30 #define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
31 #define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
32 #define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
34 #define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
35 #define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
36 #define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
37 #define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
39 #define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
40 #define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp()
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
49 nvkm_mask(fb->subdev.device, 0x10033c, 0x00008000, 0x00000000); in nv40_fb_init()
/Linux-v6.1/arch/arm/configs/
Dlpc18xx_defconfig21 CONFIG_DRAM_BASE=0x28000000
22 CONFIG_DRAM_SIZE=0x02000000
23 CONFIG_FLASH_MEM_BASE=0x1b000000
24 CONFIG_FLASH_SIZE=0x00080000
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dmediatek-pcie.txt32 where N starting from 0 to one less than the number of root ports.
80 reg = <0 0x1a000000 0 0x1000>;
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
Dbrcm,iproc-pcie.yaml127 reg = <0x18012000 0x1000>;
130 interrupt-map-mask = <0 0 0 0>;
131 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
133 linux,pci-domain = <0>;
135 bus-range = <0x00 0xff>;
140 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
141 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
143 phys = <&phy 0 5>;
147 brcm,pcie-ob-axi-offset = <0x00000000>;
165 reg = <0x18013000 0x1000>;
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/Linux-v6.1/drivers/soc/tegra/cbb/
Dtegra194-cbb.c30 #define ERRLOGGER_0_ID_COREID_0 0x00000000
31 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
32 #define ERRLOGGER_0_FAULTEN_0 0x00000008
33 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
34 #define ERRLOGGER_0_ERRCLR_0 0x00000010
35 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
36 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
37 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
38 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
39 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi17 bus@0 {
22 ranges = <0x0 0x0 0x0 0x40000000>;
27 reg = <0x2600000 0x210000>;
75 ranges = <0x02900000 0x02900000 0x200000>;
80 reg = <0x02900800 0x800>;
87 ranges = <0x02900800 0x02900800 0x11800>;
93 reg = <0x2901000 0x100>;
107 reg = <0x2901100 0x100>;
121 reg = <0x2901200 0x100>;
135 reg = <0x2901300 0x100>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx93.dtsi43 #size-cells = <0>;
45 A55_0: cpu@0 {
48 reg = <0x0>;
56 reg = <0x100>;
65 #clock-cells = <0>;
72 #clock-cells = <0>;
79 #clock-cells = <0>;
107 reg = <0 0x48000000 0 0x10000>,
108 <0 0x48040000 0 0xc0000>;
115 soc@0 {
[all …]
Dimx8mq-tqma8mq.dtsi15 reg = <0x00000000 0x40000000 0 0x40000000>;
36 pinctrl-0 = <&pinctrl_dvfs>;
43 states = <900000 0x1 1000000 0x0>;
56 size = <0 0x28000000>;
58 alloc-ranges = <0 0x40000000 0 0x78000000>;
95 pinctrl-0 = <&pinctrl_i2c1>;
104 reg = <0x8>;
199 reg = <0x1b>;
204 reg = <0x51>;
206 pinctrl-0 = <&pinctrl_rtc>;
[all …]
/Linux-v6.1/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/Linux-v6.1/arch/arm/mach-versatile/
Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/Linux-v6.1/drivers/gpu/drm/etnaviv/
Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]

123