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/Linux-v5.10/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358775.yaml28 description: i2c address of the bridge, 0x0f
57 const: 0
59 port@0:
76 - port@0
99 reg = <0x078b8000 0x500>;
102 #size-cells = <0>;
106 reg = <0x0f>;
116 #size-cells = <0>;
118 port@0 {
119 reg = <0>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/thermal/
Dti,am654-thermal.yaml38 reg = <0x42050000 0x25c>;
46 thermal-sensors = <&vtm0 0>;
/Linux-v5.10/arch/arm/boot/dts/
Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
Dbcm7445.dtsi17 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
50 reg = <0x00 0xffd01000 0x00 0x1000>,
51 <0x00 0xffd02000 0x00 0x2000>,
52 <0x00 0xffd04000 0x00 0x2000>,
53 <0x00 0xffd06000 0x00 0x2000>;
70 ranges = <0 0x00 0xf0000000 0x1000000>;
74 reg = <0x40ab00 0x20>;
84 reg = <0x404000 0x51c>;
[all …]
/Linux-v5.10/drivers/clk/meson/
Daxg.h19 #define HHI_MIPI_CNTL0 0x00
20 #define HHI_GP0_PLL_CNTL 0x40
21 #define HHI_GP0_PLL_CNTL2 0x44
22 #define HHI_GP0_PLL_CNTL3 0x48
23 #define HHI_GP0_PLL_CNTL4 0x4c
24 #define HHI_GP0_PLL_CNTL5 0x50
25 #define HHI_GP0_PLL_STS 0x54
26 #define HHI_GP0_PLL_CNTL1 0x58
27 #define HHI_HIFI_PLL_CNTL 0x80
28 #define HHI_HIFI_PLL_CNTL2 0x84
[all …]
Dg12a.h20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
Dmeson8b.h16 * Register offsets from the HardKernel[0] data sheet are listed in comment
20 * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
22 #define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
23 #define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
24 #define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
25 #define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */
26 #define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
27 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
29 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
[all …]
Dgxbb.h17 #define SCR 0x2C /* 0x0b offset in data sheet */
18 #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
20 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
21 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
22 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
23 #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
24 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
25 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
27 #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
28 #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
[all …]
/Linux-v5.10/arch/arm64/boot/dts/ti/
Dk3-am65-wakeup.dtsi39 reg = <0x43000014 0x4>;
44 reg = <0x4301c000 0x118>;
47 pinctrl-single,function-mask = <0xffffffff>;
52 reg = <0x42300000 0x100>;
63 reg = <0x42120000 0x100>;
66 #size-cells = <0>;
80 ti,interrupt-ranges = <0 712 16>;
85 reg = <0x42110000 0x100>;
93 ti,davinci-gpio-unbanked = <0>;
94 clocks = <&k3_clks 59 0>;
[all …]
/Linux-v5.10/arch/arm/include/asm/
Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
17 #define V7M_SCB_VTOR 0x08
19 #define V7M_SCB_AIRCR 0x0c
20 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
23 #define V7M_SCB_SCR 0x10
26 #define V7M_SCB_CCR 0x14
[all …]
/Linux-v5.10/arch/mips/include/asm/netlogic/xlp-hal/
Dpcibus.h39 #define PCIE_MEM_BASE 0xd0000000ULL
40 #define PCIE_MEM_LIMIT 0xdfffffffULL
41 #define PCIE_IO_BASE 0x14000000ULL
42 #define PCIE_IO_LIMIT 0x15ffffffULL
44 #define PCIE_BRIDGE_CMD 0x1
45 #define PCIE_BRIDGE_MSI_CAP 0x14
46 #define PCIE_BRIDGE_MSI_ADDRL 0x15
47 #define PCIE_BRIDGE_MSI_ADDRH 0x16
48 #define PCIE_BRIDGE_MSI_DATA 0x17
51 #define PCIE_BYTE_SWAP_MEM_BASE 0x247
[all …]
/Linux-v5.10/tools/perf/arch/powerpc/util/
Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/Linux-v5.10/drivers/gpu/drm/rockchip/
Drk3066_hdmi.h10 #define GRF_SOC_CON0 0x150
13 #define DDC_SEGMENT_ADDR 0x30
15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
17 #define N_32K 0x1000
18 #define N_441K 0x1880
19 #define N_882K 0x3100
20 #define N_1764K 0x6200
21 #define N_48K 0x1800
22 #define N_96K 0x3000
23 #define N_192K 0x6000
[all …]
/Linux-v5.10/drivers/media/pci/tw68/
Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
[all …]
/Linux-v5.10/arch/arm/mach-mmp/
Dmmp2.c32 #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
36 MFP_ADDR_X(GPIO0, GPIO58, 0x54),
37 MFP_ADDR_X(GPIO59, GPIO73, 0x280),
38 MFP_ADDR_X(GPIO74, GPIO101, 0x170),
40 MFP_ADDR(GPIO102, 0x0),
41 MFP_ADDR(GPIO103, 0x4),
42 MFP_ADDR(GPIO104, 0x1fc),
43 MFP_ADDR(GPIO105, 0x1f8),
44 MFP_ADDR(GPIO106, 0x1f4),
45 MFP_ADDR(GPIO107, 0x1f0),
[all …]
/Linux-v5.10/arch/arm/mach-ux500/
Dpm.c22 #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
23 #define PRCM_ARM_WFI_STANDBY_WFI0 0x08
24 #define PRCM_ARM_WFI_STANDBY_WFI1 0x10
25 #define PRCM_IOCR (prcmu_base + 0x310)
26 #define PRCM_IOCR_IOFORCE 0x1
29 #define PRCM_A9_MASK_REQ (prcmu_base + 0x328)
30 #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
32 #define PRCM_A9_MASK_ACK (prcmu_base + 0x32c)
33 #define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c)
34 #define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120)
[all …]
/Linux-v5.10/drivers/gpu/drm/mediatek/
Dmtk_hdmi_regs.h9 #define GRL_INT_MASK 0x18
10 #define GRL_IFM_PORT 0x188
11 #define GRL_CH_SWAP 0x198
12 #define LR_SWAP BIT(0)
17 #define GRL_I2S_C_STA0 0x140
18 #define GRL_I2S_C_STA1 0x144
19 #define GRL_I2S_C_STA2 0x148
20 #define GRL_I2S_C_STA3 0x14C
21 #define GRL_I2S_C_STA4 0x150
22 #define GRL_I2S_UV 0x154
[all …]
/Linux-v5.10/arch/arc/include/asm/
Dperf_event.h15 #define ARC_REG_CC_BUILD 0xF6
16 #define ARC_REG_CC_INDEX 0x240
17 #define ARC_REG_CC_NAME0 0x241
18 #define ARC_REG_CC_NAME1 0x242
20 #define ARC_REG_PCT_BUILD 0xF5
21 #define ARC_REG_PCT_COUNTL 0x250
22 #define ARC_REG_PCT_COUNTH 0x251
23 #define ARC_REG_PCT_SNAPL 0x252
24 #define ARC_REG_PCT_SNAPH 0x253
25 #define ARC_REG_PCT_CONFIG 0x254
[all …]
/Linux-v5.10/drivers/phy/samsung/
Dphy-exynos-pcie.c24 #define PCIE_PHY_GLOBAL_RESET 0x000
25 #define PCIE_PHY_COMMON_RESET 0x004
26 #define PCIE_PHY_CMN_REG 0x008
27 #define PCIE_PHY_MAC_RESET 0x00c
28 #define PCIE_PHY_PLL_LOCKED 0x010
29 #define PCIE_PHY_TRSVREG_RESET 0x020
30 #define PCIE_PHY_TRSV_RESET 0x024
33 #define PCIE_PHY_IMPEDANCE 0x004
34 #define PCIE_PHY_PLL_DIV_0 0x008
35 #define PCIE_PHY_PLL_BIAS 0x00c
[all …]
/Linux-v5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_intf.c10 #define INTF_TIMING_ENGINE_EN 0x000
11 #define INTF_CONFIG 0x004
12 #define INTF_HSYNC_CTL 0x008
13 #define INTF_VSYNC_PERIOD_F0 0x00C
14 #define INTF_VSYNC_PERIOD_F1 0x010
15 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014
16 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018
17 #define INTF_DISPLAY_V_START_F0 0x01C
18 #define INTF_DISPLAY_V_START_F1 0x020
19 #define INTF_DISPLAY_V_END_F0 0x024
[all …]

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