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/Linux-v6.1/arch/arm/boot/dts/
Dwm8505.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
47 reg = <0xd8140000 0x10000>;
56 reg = <0xD8150000 0x10000>;
62 reg = <0xd8110000 0x10000>;
71 reg = <0xd8130000 0x1000>;
74 #size-cells = <0>;
77 #clock-cells = <0>;
83 #clock-cells = <0>;
[all …]
Dvt8500.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
45 reg = <0xd8140000 0x10000>;
51 reg = <0xd8110000 0x10000>;
60 reg = <0xd8130000 0x1000>;
64 #size-cells = <0>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
76 enable-reg = <0x250>;
[all …]
Dwm8750.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
49 reg = <0xd8140000 0x10000>;
58 reg = <0xD8150000 0x10000>;
64 reg = <0xd8110000 0x10000>;
73 reg = <0xd8130000 0x1000>;
77 #size-cells = <0>;
80 #clock-cells = <0>;
86 #clock-cells = <0>;
[all …]
Dwm8650.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
43 reg = <0xd8140000 0x10000>;
52 reg = <0xD8150000 0x10000>;
58 reg = <0xd8110000 0x10000>;
67 reg = <0xd8130000 0x1000>;
71 #size-cells = <0>;
74 #clock-cells = <0>;
80 #clock-cells = <0>;
[all …]
Dwm8850.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
26 reg = <0x0 0x0>;
46 reg = <0xd8140000 0x10000>;
55 reg = <0xD8150000 0x10000>;
61 reg = <0xd8110000 0x10000>;
70 reg = <0xd8130000 0x1000>;
74 #size-cells = <0>;
77 #clock-cells = <0>;
[all …]
Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
/Linux-v6.1/Documentation/sound/cards/
Dmultisound.sh77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card
96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary
107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil
108 # synth to 0x330 and irq 9 (may need editing for your system):
110 # (READPORT 0x0203)
115 # (CONFIGURE BVJ0440/-1 (LD 0
116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000))
121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E)))
140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it
143 # on the card to 0x250, 0x260 or 0x270).
[all …]
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt6795-apmixedsys.c13 #define REG_REF2USB 0x8
14 #define REG_AP_PLL_CON7 0x1c
15 #define MD1_MTCMOS_OFF BIT(0)
21 #define MT6795_CON0_EN BIT(0)
41 .pll_en_bit = 0, \
45 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
46 21, 0x204, 24, 0x0, 0x204, 0),
47 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
48 21, 0x220, 4, 0x0, 0x224, 0),
49 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
[all …]
/Linux-v6.1/Documentation/locking/
Dlockstat.rst56 - shortest (non-0) time we ever had to wait for a lock
69 - shortest (non-0) time we ever held the lock
97 # echo 0 >/proc/sys/kernel/lock_stat
114 … &mm->mmap_sem 1 [<ffffffff811502a7>] khugepaged_scan_mm_slot+0x57/0x280
115 … &mm->mmap_sem 96 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
116 … &mm->mmap_sem 34 [<ffffffff81113d77>] vm_mmap_pgoff+0x87/0xd0
117 … &mm->mmap_sem 17 [<ffffffff81127e71>] vm_munmap+0x41/0x80
119 … &mm->mmap_sem 1 [<ffffffff81046fda>] dup_mmap+0x2a/0x3f0
120 … &mm->mmap_sem 60 [<ffffffff81129e29>] SyS_mprotect+0xe9/0x250
121 … &mm->mmap_sem 41 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/Linux-v6.1/sound/isa/gus/
Dgusclassic.c27 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
30 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x230,0x240,0x250,0x260 */
34 static int joystick_dac[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 29};
35 /* 0 to 31, (0.59V-4.52V or 0.389V-2.98V) */
36 static int channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 24};
37 static int pcm_channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
69 static const long possible_ports[] = {0x220, 0x230, 0x240, 0x250, 0x260}; in snd_gusclassic_create()
77 if (irq[n] < 0) { in snd_gusclassic_create()
84 if (dma1[n] < 0) { in snd_gusclassic_create()
91 if (dma2[n] < 0) { in snd_gusclassic_create()
[all …]
Dgusmax.c25 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
28 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x230,0x240,0x250,0x260 */
32 static int joystick_dac[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 29};
33 /* 0 to 31, (0.59V-4.52V or 0.389V-2.98V) */
34 static int channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 24};
35 static int pcm_channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
73 snd_gf1_i_write8(gus, SNDRV_GF1_GB_RESET, 0); /* reset GF1 */ in snd_gusmax_detect()
75 if ((d & 0x07) != 0) { in snd_gusmax_detect()
76 snd_printdd("[0x%lx] check 1 failed - 0x%x\n", gus->gf1.port, d); in snd_gusmax_detect()
83 if ((d & 0x07) != 1) { in snd_gusmax_detect()
[all …]
/Linux-v6.1/include/soc/tegra/
Dfuse.h11 #define TEGRA20 0x20
12 #define TEGRA30 0x30
13 #define TEGRA114 0x35
14 #define TEGRA124 0x40
15 #define TEGRA132 0x13
16 #define TEGRA210 0x21
17 #define TEGRA186 0x18
18 #define TEGRA194 0x19
19 #define TEGRA234 0x23
21 #define TEGRA_FUSE_SKU_CALIB_0 0xf0
[all …]
/Linux-v6.1/drivers/net/ethernet/sunplus/
Dspl2sw_register.h10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
[all …]
/Linux-v6.1/arch/arc/include/asm/
Dperf_event.h15 #define ARC_REG_CC_BUILD 0xF6
16 #define ARC_REG_CC_INDEX 0x240
17 #define ARC_REG_CC_NAME0 0x241
18 #define ARC_REG_CC_NAME1 0x242
20 #define ARC_REG_PCT_BUILD 0xF5
21 #define ARC_REG_PCT_COUNTL 0x250
22 #define ARC_REG_PCT_COUNTH 0x251
23 #define ARC_REG_PCT_SNAPL 0x252
24 #define ARC_REG_PCT_SNAPH 0x253
25 #define ARC_REG_PCT_CONFIG 0x254
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dbrcm,mdio-mux-iproc.yaml43 reg = <0x66020000 0x250>;
45 #size-cells = <0>;
47 mdio@0 {
48 reg = <0x0>;
50 #size-cells = <0>;
52 pci_phy0: pci-phy@0 {
54 reg = <0x0>;
55 #phy-cells = <0>;
60 reg = <0x7>;
62 #size-cells = <0>;
[all …]
/Linux-v6.1/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/Linux-v6.1/tools/perf/tests/
Dmem2node.c17 { .node = 0, .map = "0" },
52 .memory_nodes = (struct memory_node *) &nodes[0], in test__mem2node()
54 .memory_bsize = 0x100, in test__mem2node()
58 for (i = 0; i < ARRAY_SIZE(nodes); i++) { in test__mem2node()
67 T("failed: mem2node__node", 0 == mem2node__node(&map, 0x50)); in test__mem2node()
68 T("failed: mem2node__node", 1 == mem2node__node(&map, 0x100)); in test__mem2node()
69 T("failed: mem2node__node", 1 == mem2node__node(&map, 0x250)); in test__mem2node()
70 T("failed: mem2node__node", 3 == mem2node__node(&map, 0x500)); in test__mem2node()
71 T("failed: mem2node__node", 3 == mem2node__node(&map, 0x650)); in test__mem2node()
72 T("failed: mem2node__node", -1 == mem2node__node(&map, 0x450)); in test__mem2node()
[all …]
/Linux-v6.1/drivers/clk/renesas/
Dr8a77995-cpg-mssr.c109 DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
110 DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
115 DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
116 DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
212 * 0 48 x 1 x250/4 x100/3 x100/3
213 * 1 48 x 1 x250/4 x100/3 x58/3
235 return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode); in r8a77995_cpg_mssr_init()
/Linux-v6.1/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-pinctrl.dtsi37 reg = <0x00140000 0x250>;
45 reg = <0x0014029c 0x26c>;
49 pinctrl-single,function-mask = <0xf>;
51 &range 0 91 MODE_GPIO
61 0x038 MODE_NITRO /* tsio_0 */
62 0x03c MODE_NITRO /* tsio_1 */
68 0x0ac MODE_PNOR /* nand_ce1_n */
69 0x0b0 MODE_PNOR /* nand_ce0_n */
70 0x0b4 MODE_PNOR /* nand_we_n */
71 0x0b8 MODE_PNOR /* nand_wp_n */
[all …]
/Linux-v6.1/drivers/scsi/mvsas/
Dmv_94xx.h18 VANIR_A0_REV = 0xA0,
19 VANIR_B0_REV = 0x01,
20 VANIR_C0_REV = 0x02,
21 VANIR_C1_REV = 0x03,
22 VANIR_C2_REV = 0xC2,
26 MVS_HST_CHIP_CONFIG = 0x10104, /* chip configuration */
30 MVS_GBL_CTL = 0x04, /* global control */
31 MVS_GBL_INT_STAT = 0x00, /* global irq status */
32 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
34 MVS_PHY_CTL = 0x40, /* SOC PHY Control */
[all …]
/Linux-v6.1/drivers/pinctrl/
Dpinctrl-pic32.h12 #define ANSEL_REG 0x00
13 #define TRIS_REG 0x10
14 #define PORT_REG 0x20
15 #define LAT_REG 0x30
16 #define ODCU_REG 0x40
17 #define CNPU_REG 0x50
18 #define CNPD_REG 0x60
19 #define CNCON_REG 0x70
20 #define CNEN_REG 0x80
21 #define CNSTAT_REG 0x90
[all …]

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