Searched +full:0 +full:x2210000 (Results 1 – 6 of 6) sorted by relevance
| /Linux-v6.1/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls2080a-simu.dts | 21 reg = <0x0 0x2210000 0x0 0x100>;
22 interrupts = <0 58 0x1>;
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| /Linux-v6.1/Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 122 - Bit 0 specifies polarity
123 - 0: Active-high (normal).
137 - Bits [3:0] indicate trigger type and level:
190 reg = <0x2200000 0x10000>,
191 <0x2210000 0x10000>;
192 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>,
193 <0 50 IRQ_TYPE_LEVEL_HIGH>,
194 <0 53 IRQ_TYPE_LEVEL_HIGH>,
195 <0 56 IRQ_TYPE_LEVEL_HIGH>,
196 <0 59 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/ti/ |
| D | k3-j7200-main.dtsi | 10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
[all …]
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| D | k3-j721e-main.dtsi | 14 #clock-cells = <0>;
16 clock-frequency = <0>;
20 #clock-cells = <0>;
22 clock-frequency = <0>;
29 reg = <0x0 0x70000000 0x0 0x800000>;
32 ranges = <0x0 0x0 0x70000000 0x800000>;
34 atf-sram@0 {
35 reg = <0x0 0x20000>;
41 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
44 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/nvidia/ |
| D | tegra186.dtsi | 20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
127 ranges = <0x02900000 0x0 0x02900000 0x200000>;
132 reg = <0x02930000 0x20000>;
134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | tegra194.dtsi | 20 bus@0 {
24 ranges = <0x0 0x0 0x0 0x40000000>;
28 reg = <0x00100000 0xf000>,
29 <0x0010f000 0x1000>;
35 reg = <0x2200000 0x10000>,
36 <0x2210000 0x10000>;
93 reg = <0x02300000 0x1000>;
103 reg = <0x2390000 0x1000>,
104 <0x23a0000 0x1000>,
105 <0x23b0000 0x1000>,
[all …]
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