Searched +full:0 +full:x2040000 (Results 1 – 6 of 6) sorted by relevance
74 reg = <0x1f059000 0x1000>,75 <0x1d000000 0x2040000>;
11 reg = <0x00 0x70000000 0x00 0x100000>;14 ranges = <0x00 0x00 0x70000000 0x100000>;16 atf-sram@0 {17 reg = <0x00 0x20000>;23 reg = <0x00 0x00100000 0x00 0x1c000>;26 ranges = <0x00 0x00 0x00100000 0x1c000>;31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */[all …]
14 reg = <0x0 0x70000000 0x0 0x800000>;17 ranges = <0x0 0x0 0x70000000 0x800000>;19 atf-sram@0 {20 reg = <0x0 0x20000>;26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */29 ranges = <0x0 0x0 0x00100000 0x1c000>;33 reg = <0x00004070 0x4>;36 ranges = <0x4070 0x4070 0x4>;41 reg = <0x00004074 0x4>;44 ranges = <0x4074 0x4074 0x4>;[all …]
26 #size-cells = <0>;28 cpu0: cpu@0 {31 reg = <0x0>;33 clocks = <&clockgen 1 0>;42 reg = <0x1>;44 clocks = <&clockgen 1 0>;65 arm,psci-suspend-param = <0x0>;74 #clock-cells = <0>;81 #clock-cells = <0>;88 reg = <0x0 0xf1f0000 0x0 0xffff>;[all …]
11 /memreserve/ 0x80000000 0x00010000;25 #size-cells = <0>;28 cpu0: cpu@0 {32 reg = <0x0>;33 clocks = <&clockgen 1 0>;34 d-cache-size = <0x8000>;37 i-cache-size = <0xC000>;49 reg = <0x1>;50 clocks = <&clockgen 1 0>;51 d-cache-size = <0x8000>;[all …]
37 * Generated by: IDF:x 1.3.056 #define ATV_COMM_EXEC__A 0xC0000058 #define ATV_COMM_EXEC__M 0x359 #define ATV_COMM_EXEC__PRE 0x060 #define ATV_COMM_EXEC_STOP 0x061 #define ATV_COMM_EXEC_ACTIVE 0x162 #define ATV_COMM_EXEC_HOLD 0x264 #define ATV_COMM_STATE__A 0xC0000166 #define ATV_COMM_STATE__M 0xFFFF67 #define ATV_COMM_STATE__PRE 0x0[all …]
