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/Linux-v6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_6_0_sm8250.h12 .max_mixer_blendstages = 0xb,
24 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_7_0_sm8350.h12 .max_mixer_blendstages = 0xb,
24 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_6_2_sc7180.h12 .max_mixer_blendstages = 0x9,
22 .base = 0x0, .len = 0x494,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
35 .base = 0x1000, .len = 0x1dc,
40 .base = 0x1200, .len = 0x1dc,
45 .base = 0x1400, .len = 0x1dc,
[all …]
Ddpu_6_4_sm6350.h13 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
37 .base = 0x1000, .len = 0x1dc,
42 .base = 0x1200, .len = 0x1dc,
47 .base = 0x1400, .len = 0x1dc,
[all …]
Ddpu_7_2_sc7280.h12 .max_mixer_blendstages = 0x7,
22 .base = 0x0, .len = 0x2014,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
35 .base = 0x15000, .len = 0x1e8,
40 .base = 0x16000, .len = 0x1e8,
45 .base = 0x17000, .len = 0x1e8,
[all …]
Ddpu_6_5_qcm2290.h12 .max_mixer_blendstages = 0x4,
21 .base = 0x0, .len = 0x494,
23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 .base = 0x1000, .len = 0x1dc,
40 .base = 0x4000, .len = 0x1f8,
43 .xin_id = 0,
48 .base = 0x24000, .len = 0x1f8,
60 .base = 0x44000, .len = 0x320,
71 .base = 0x54000, .len = 0x1800,
[all …]
Ddpu_6_3_sm6115.h12 .max_mixer_blendstages = 0x4,
22 .base = 0x0, .len = 0x494,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 .base = 0x1000, .len = 0x1dc,
41 .base = 0x4000, .len = 0x1f8,
44 .xin_id = 0,
49 .base = 0x24000, .len = 0x1f8,
61 .base = 0x44000, .len = 0x320,
72 .base = 0x54000, .len = 0x1800,
[all …]
Ddpu_6_9_sm6375.h13 .max_mixer_blendstages = 0x4,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 .base = 0x1000, .len = 0x1dc,
42 .base = 0x4000, .len = 0x1f8,
45 .xin_id = 0,
50 .base = 0x24000, .len = 0x1f8,
62 .base = 0x44000, .len = 0x320,
65 .lm_pair = 0,
[all …]
/Linux-v6.6/drivers/clk/hisilicon/
Dclk-hi3620.c66 { HI3620_OSC32K, "osc32k", NULL, 0, 32768, },
67 { HI3620_OSC26M, "osc26m", NULL, 0, 26000000, },
68 { HI3620_PCLK, "pclk", NULL, 0, 26000000, },
69 { HI3620_PLL_ARM0, "armpll0", NULL, 0, 1600000000, },
70 { HI3620_PLL_ARM1, "armpll1", NULL, 0, 1600000000, },
71 { HI3620_PLL_PERI, "armpll2", NULL, 0, 1440000000, },
72 { HI3620_PLL_USB, "armpll3", NULL, 0, 1440000000, },
73 { HI3620_PLL_HDMI, "armpll4", NULL, 0, 1188000000, },
74 { HI3620_PLL_GPU, "armpll5", NULL, 0, 1300000000, },
79 { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, },
[all …]
/Linux-v6.6/arch/arm64/include/asm/
Dfpsimdmacros.h12 stp q0, q1, [\state, #16 * 0]
48 ldp q0, q1, [\state, #16 * 0]
73 .if (\nr) < 0 || (\nr) > 30
79 .if (\znr) < 0 || (\znr) > 31
85 .if (\pnr) < 0 || (\pnr) > 15
106 .macro _sve_str_v nz, nxbase, offset=0
109 _check_num (\offset), -0x100, 0xff
110 .inst 0xe5804000 \
114 | (((\offset) & 0x1f8) << 13)
118 .macro _sve_ldr_v nz, nxbase, offset=0
[all …]
/Linux-v6.6/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcs-v6_20.h10 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
11 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
12 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
13 #define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
14 #define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
15 #define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
16 #define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
Dphy-qcom-qmp-qserdes-txrx-v6_20.h9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
Dphy-qcom-qmp-qserdes-txrx-v6.h9 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
11 #define QSERDES_V6_TX_TX_DRV_LVL 0x14
12 #define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
13 #define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
14 #define QSERDES_V6_TX_TX_BAND 0x24
15 #define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
16 #define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
17 #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
18 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
[all …]
Dphy-qcom-qmp-qserdes-com-v6.h11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00
12 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04
13 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x10
14 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14
15 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18
16 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c
17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20
18 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24
19 #define QSERDES_V6_COM_DEC_START_MODE1 0x28
20 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
/Linux-v6.6/arch/powerpc/lib/
Dldstfp.S26 rlwinm r3,r3,3,0xf8
28 reg = 0
30 stfd reg, 0(r4)
50 rlwinm r3,r3,3,0xf8
52 reg = 0
54 lfd reg, 0(r4)
75 rlwinm r3,r3,3,0xf8
77 reg = 0
79 stvx reg, 0, r4
99 rlwinm r3,r3,3,0xf8
[all …]
/Linux-v6.6/tools/testing/selftests/kvm/lib/x86_64/
Dsvm.c48 memset(svm->msr_hva, 0, getpagesize()); in vcpu_alloc_svm()
79 memset(vmcb, 0, sizeof(*vmcb)); in generic_svm_setup()
80 asm volatile ("vmsave %0\n\t" : : "a" (vmcb_gpa) : "memory"); in generic_svm_setup()
81 vmcb_set_seg(&save->es, get_es(), 0, -1U, data_seg_attr); in generic_svm_setup()
82 vmcb_set_seg(&save->cs, get_cs(), 0, -1U, code_seg_attr); in generic_svm_setup()
83 vmcb_set_seg(&save->ss, get_ss(), 0, -1U, data_seg_attr); in generic_svm_setup()
84 vmcb_set_seg(&save->ds, get_ds(), 0, -1U, data_seg_attr); in generic_svm_setup()
85 vmcb_set_seg(&save->gdtr, 0, get_gdt().address, get_gdt().size, 0); in generic_svm_setup()
86 vmcb_set_seg(&save->idtr, 0, get_idt().address, get_idt().size, 0); in generic_svm_setup()
89 save->cpl = 0; in generic_svm_setup()
[all …]
/Linux-v6.6/arch/powerpc/xmon/
Dspu-opc.c20 …QUAD WORD (0,RC,RB,RA,RT) latency …
21 APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form
/Linux-v6.6/include/dt-bindings/clock/
Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/Linux-v6.6/arch/sh/drivers/pci/
Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/pinctrl/
Dti,iodelay.txt24 reg = <0x4844a000 0x0d1c>;
26 #size-cells = <0>;
35 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
36 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
37 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
38 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
40 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
41 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
42 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
[all …]
Dfsl,imx93-pinctrl.yaml76 reg = <0x30330000 0x10000>;
80 <0x48 0x1f8 0x41c 0x1 0x0 0x49>,
81 <0x4c 0x1fc 0x418 0x1 0x0 0x49>;
/Linux-v6.6/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt6 - #size-cells: 32bit valued, 0 cell.
24 Valid value are 0, 1, 2, or 3 (for spdif)
30 #size-cells = <0>;
31 reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>;
42 <0>,
43 <0>,
44 <0>;
48 ssp0: ssp_port@0 {
49 reg = <0>;

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