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/Linux-v5.15/arch/sparc/include/asm/
Dobio.h3 * obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
18 * | 0xFE | DEVID | | XDBUS ID | |
20 * 35 28 27 20 19 10 9 8 7 0
23 #define CSR_BASE_ADDR 0xe0000000
31 * | 0xF | DEVID[7:1] | |
33 * 35 32 31 25 24 0
36 #define ECSR_BASE_ADDR 0x00000000
44 #define BW_LOCAL_BASE 0xfff00000
46 #define BW_CID 0x00000000
47 #define BW_DBUS_CTRL 0x00000008
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mtd/partitions/
Dbrcm,bcm4908-partitions.yaml31 "^partition@[0-9a-f]+$":
51 partition@0 {
53 reg = <0x0 0x100000>;
58 reg = <0x100000 0xf00000>;
63 reg = <0x1000000 0xf00000>;
68 reg = <0x1f00000 0x100000>;
/Linux-v5.15/drivers/misc/habanalabs/include/gaudi/asic_reg/
Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dnic0_qm0_masks.h23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
/Linux-v5.15/arch/mips/boot/dts/ingenic/
Drs90.dts16 reg = <0x0 0x2000000>;
26 reg = <0x1f00000 0x100000>;
42 pwms = <&pwm 3 40000 0>;
44 brightness-levels = <0 16 32 48 64 80 112 144 192 255>;
48 pinctrl-0 = <&pins_pwm3>;
53 keys@0 {
56 #size-cells = <0>;
58 key@0 {
115 key@0 {
171 #phy-cells = <0>;
[all …]
/Linux-v5.15/drivers/input/joystick/
Dcobra.c29 …START, BTN_SELECT, BTN_TL, BTN_TR, BTN_X, BTN_Y, BTN_Z, BTN_A, BTN_B, BTN_C, BTN_TL2, BTN_TR2, 0 };
50 for (i = 0; i < 2; i++) { in cobra_read_packet()
51 r[i] = buf[i] = 0; in cobra_read_packet()
60 t[0]--; t[1]--; in cobra_read_packet()
62 for (i = 0, w = u ^ v; i < 2 && w; i++, w >>= 2) in cobra_read_packet()
63 if (w & 0x30) { in cobra_read_packet()
64 if ((w & 0x30) < 0x30 && r[i] < COBRA_LENGTH && t[i] > 0) { in cobra_read_packet()
68 } else t[i] = 0; in cobra_read_packet()
70 } while (t[0] > 0 || t[1] > 0); in cobra_read_packet()
74 ret = 0; in cobra_read_packet()
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dnuvoton-npcm730-gsj.dts35 reg = <0 0x40000000>;
47 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
135 pinctrl-0 = <&spi0cs1_pins>;
138 spi-nor@0 {
142 reg = <0>;
149 bmc@0{
151 reg = <0x000000 0x2000000>;
153 u-boot@0 {
155 reg = <0x0000000 0x80000>;
160 reg = <0x00100000 0x40000>;
[all …]
Dls1021a.dtsi74 #size-cells = <0>;
79 reg = <0xf00>;
80 clocks = <&clockgen 1 0>;
87 reg = <0xf01>;
88 clocks = <&clockgen 1 0>;
95 reg = <0x0 0x0 0x0 0x0>;
100 #clock-cells = <0>;
123 offset = <0xb0>;
124 mask = <0x02>;
137 reg = <0x0 0x1080000 0x0 0x1000>;
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dmpc8379_mds.dts26 #size-cells = <0>;
28 PowerPC,8379@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x20000000>; // 512MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
55 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
Dmpc8378_mds.dts28 #size-cells = <0>;
30 PowerPC,8378@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
57 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
Dmpc8377_mds.dts28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
57 ranges = <0 0x0 0xfe000000 0x02000000
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
85 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
[all …]
Dfsl-ls1043a.dtsi36 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0x0>;
48 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
57 reg = <0x1>;
58 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
67 reg = <0x2>;
68 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
77 reg = <0x3>;
78 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
Dfsl-ls1046a.dtsi37 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 reg = <0x1>;
53 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 reg = <0x2>;
63 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
72 reg = <0x3>;
73 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
/Linux-v5.15/drivers/net/ethernet/qlogic/qed/
Dqed_init_ops.c25 0,
26 0,
27 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
28 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
29 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
30 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
31 0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
32 0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
33 0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
34 0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
[all …]
/Linux-v5.15/arch/mips/lantiq/xway/
Dsysctrl.c22 #define CGU_IFCCR 0x0018
23 #define CGU_IFCCR_VR9 0x0024
25 #define CGU_SYS 0x0010
27 #define CGU_PCICR 0x0034
28 #define CGU_PCICR_VR9 0x0038
30 #define CGU_EPHY 0x10
34 #define PMU_PWDCR 0x1C
36 #define PMU_PWDSR 0x20
38 #define PMU_PWDCR1 0x24
40 #define PMU_PWDSR1 0x28
[all …]
/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dmsm8994.dtsi20 #clock-cells = <0>;
27 #clock-cells = <0>;
35 #size-cells = <0>;
37 CPU0: cpu@0 {
40 reg = <0x0 0x0>;
52 reg = <0x0 0x1>;
60 reg = <0x0 0x2>;
68 reg = <0x0 0x3>;
76 reg = <0x0 0x100>;
88 reg = <0x0 0x101>;
[all …]
/Linux-v5.15/include/linux/qed/
Dcommon_hsi.h16 #define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
23 } while (0)
47 #define ISCSI_CDU_TASK_SEG_TYPE 0
48 #define FCOE_CDU_TASK_SEG_TYPE 0
59 #define YSTORM_QZONE_SIZE 0
60 #define PSTORM_QZONE_SIZE 0
94 #define FW_ENGINEERING_VERSION 0
154 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
157 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
159 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/Linux-v5.15/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hw.c15 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
19 #define CRB_BLK(off) ((off >> 20) & 0x3f)
20 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
21 #define CRB_WINDOW_2M (0x130060)
22 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
23 #define CRB_INDIRECT_2M (0x1e0000UL)
52 {{{0, 0, 0, 0} } }, /* 0: PCI */
53 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
54 {1, 0x0110000, 0x0120000, 0x130000},
55 {1, 0x0120000, 0x0122000, 0x124000},
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]

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