Searched +full:0 +full:x1f0000 (Results 1 – 25 of 79) sorted by relevance
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| /Linux-v5.15/drivers/net/ethernet/qualcomm/emac/ |
| D | emac-phy.c | 15 #define EMAC_MDIO_CTRL 0x001414
16 #define EMAC_PHY_STS 0x001418
17 #define EMAC_MDIO_EX_CTRL 0x001440
24 #define MDIO_CLK_SEL_BMSK 0x7000000
29 #define MDIO_REG_ADDR_BMSK 0x1f0000
31 #define MDIO_DATA_BMSK 0xffff
32 #define MDIO_DATA_SHFT 0
35 #define PHY_ADDR_BMSK 0x1f0000
38 #define MDIO_CLK_25_4 0
88 return 0; in emac_mdio_write()
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| /Linux-v5.15/drivers/media/rc/ |
| D | ir-sony-decoder.c | 44 return 0; in ir_sony_decode()
62 data->count = 0; in ir_sony_decode()
64 return 0; in ir_sony_decode()
74 return 0; in ir_sony_decode()
88 return 0; in ir_sony_decode()
101 return 0; in ir_sony_decode()
119 device = bitrev8((data->bits << 3) & 0xF8); in ir_sony_decode()
120 subdevice = 0; in ir_sony_decode()
121 function = bitrev8((data->bits >> 4) & 0xFE); in ir_sony_decode()
128 device = bitrev8((data->bits >> 0) & 0xFF); in ir_sony_decode()
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| D | ir-rc5-decoder.c | 50 return 0; in ir_rc5_decode()
61 return 0; in ir_rc5_decode()
88 return 0; in ir_rc5_decode()
117 return 0; in ir_rc5_decode()
119 xdata = (data->bits & 0x0003F) >> 0; in ir_rc5_decode()
120 command = (data->bits & 0x00FC0) >> 6; in ir_rc5_decode()
121 system = (data->bits & 0x1F000) >> 12; in ir_rc5_decode()
122 toggle = (data->bits & 0x20000) ? 1 : 0; in ir_rc5_decode()
123 command += (data->bits & 0x40000) ? 0 : 0x40; in ir_rc5_decode()
132 return 0; in ir_rc5_decode()
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| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc-sc7180.yaml | 68 reg = <0x00100000 0x1f0000>;
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| D | qcom,gcc-sc8180x.yaml | 67 reg = <0x00100000 0x1f0000>;
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| D | qcom,gcc-sdx55.yaml | 66 reg = <0x00100000 0x1f0000>;
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| D | qcom,gcc-sm6350.yaml | 67 reg = <0x00100000 0x1f0000>;
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| D | qcom,gcc-sm8150.yaml | 66 reg = <0x00100000 0x1f0000>;
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| D | qcom,gcc-sm8250.yaml | 66 reg = <0x00100000 0x1f0000>;
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| D | qcom,gcc-sm6115.yaml | 65 reg = <0x01400000 0x1f0000>;
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| D | qcom,gcc-sm6125.yaml | 65 reg = <0x01400000 0x1f0000>;
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| D | qcom,gcc-sdm845.yaml | 29 - description: PCIE 0 Pipe clock source
71 reg = <0x100000 0x1f0000>;
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| D | qcom,gcc-sc7280.yaml | 28 - description: PCIE-0 pipe clock source
30 - description: USF phy rx symbol 0 clock source
32 - description: USF phy tx symbol 0 clock source
75 reg = <0x00100000 0x1f0000>;
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| D | qcom,gcc-sm8350.yaml | 28 - description: PCIE 0 Pipe clock source (Optional clock)
30 - description: UFS card Rx symbol 0 clock source (Optional clock)
32 - description: UFS card Tx symbol 0 clock source (Optional clock)
33 - description: UFS phy Rx symbol 0 clock source (Optional clock)
35 - description: UFS phy Tx symbol 0 clock source (Optional clock)
85 reg = <0x00100000 0x1f0000>;
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| /Linux-v5.15/Documentation/i2c/ |
| D | i2c-stub.rst | 26 explicitly by setting the respective bits (0x03000000) in the functionality
52 value 0x1f0000 would only enable the quick, byte and byte data
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| /Linux-v5.15/drivers/misc/habanalabs/include/goya/asic_reg/ |
| D | mme_masks.h | 23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
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| D | goya_masks.h | 180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700
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| /Linux-v5.15/drivers/net/mdio/ |
| D | mdio-moxart.c | 16 #define REG_PHY_CTRL 0
22 #define REGAD_MASK 0x3e00000
23 #define PHYAD_MASK 0x1f0000
24 #define MIIRDATA_MASK 0xffff
27 #define MIIWDATA_MASK 0xffff
36 u32 ctrl = 0; in moxart_mdio_read()
54 } while (count > 0); in moxart_mdio_read()
65 u32 ctrl = 0; in moxart_mdio_write()
82 return 0; in moxart_mdio_write()
86 } while (count > 0); in moxart_mdio_write()
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| /Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
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| D | oss_2_0_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
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| D | oss_3_0_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
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| D | oss_3_0_1_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
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| /Linux-v5.15/drivers/devfreq/event/ |
| D | rockchip-dfi.c | 26 #define DDRMON_CTRL 0x04
27 #define CLR_DDRMON_CTRL (0x1f0000 << 0)
28 #define LPDDR4_EN (0x10001 << 4)
29 #define HARDWARE_EN (0x10001 << 3)
30 #define LPDDR3_EN (0x10001 << 2)
31 #define SOFTWARE_EN (0x10001 << 1)
32 #define SOFTWARE_DIS (0x10000 << 1)
33 #define TIME_CNT_EN (0x10001 << 0)
35 #define DDRMON_CH0_COUNT_NUM 0x28
36 #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
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| /Linux-v5.15/arch/arm64/boot/dts/arm/ |
| D | rtsm_ve-motherboard.dtsi | 13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
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| /Linux-v5.15/sound/soc/codecs/ |
| D | jz4740.c | 23 #define JZ4740_REG_CODEC_1 0x0
24 #define JZ4740_REG_CODEC_2 0x4
44 #define JZ4740_CODEC_1_RESET BIT(0)
55 #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
56 #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
57 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
58 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
63 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
66 { JZ4740_REG_CODEC_1, 0x021b2302 },
67 { JZ4740_REG_CODEC_2, 0x00170803 },
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