Searched +full:0 +full:x1ee0000 (Results 1 – 5 of 5) sorted by relevance
54 "^clock-controller@[0-9a-z]+$":67 reg = <0x1ee0000 0x10000>;
32 #size-cells = <0>;34 cpu0: cpu@0 {37 reg = <0x0>;38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;54 arm,psci-suspend-param = <0x0>;63 #clock-cells = <0>;70 #clock-cells = <0>;85 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */93 <0x0 0x1402000 0 0x2000>, /* GICC */[all …]
38 #size-cells = <0>;40 cpu0: cpu@0 {43 reg = <0x0>;44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;53 reg = <0x1>;54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;63 reg = <0x2>;64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;73 reg = <0x3>;74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;[all …]
37 #size-cells = <0>;45 cpu0: cpu@0 {48 reg = <0x0>;49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;58 reg = <0x1>;59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;68 reg = <0x2>;69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;78 reg = <0x3>;79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;[all …]
31 #size-cells = <0>;36 reg = <0xf00>;37 clocks = <&clockgen 1 0>;44 reg = <0xf01>;45 clocks = <&clockgen 1 0>;50 memory@0 {52 reg = <0x0 0x0 0x0 0x0>;57 #clock-cells = <0>;80 offset = <0xb0>;81 mask = <0x02>;[all …]
