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/Linux-v6.1/Documentation/admin-guide/
Dramoops.rst27 Typically the default value of ``mem_type=0`` should be used as that sets the pstore
44 ``max_reason`` should be set to 1 (KMSG_DUMP_PANIC). Setting this to 0
69 mem=128M ramoops.mem_address=0x8000000 ramoops.ecc=1
82 reg = <0 0x8f000000 0 0x100000>;
83 record-size = <0x4000>;
84 console-size = <0x4000>;
155 0 ffffffff8101ea64 ffffffff8101bcda native_apic_mem_read <- disconnect_bsp_APIC+0x6a/0xc0
156 0 ffffffff8101ea44 ffffffff8101bcf6 native_apic_mem_write <- disconnect_bsp_APIC+0x86/0xc0
157 0 ffffffff81020084 ffffffff8101a4b5 hpet_disable <- native_machine_shutdown+0x75/0x90
158 0 ffffffff81005f94 ffffffff8101a4bb iommu_shutdown_noop <- native_machine_shutdown+0x7b/0x90
[all …]
/Linux-v6.1/drivers/firewire/
Dohci.h7 #define OHCI1394_Version 0x000
8 #define OHCI1394_GUID_ROM 0x004
9 #define OHCI1394_ATRetries 0x008
10 #define OHCI1394_CSRData 0x00C
11 #define OHCI1394_CSRCompareData 0x010
12 #define OHCI1394_CSRControl 0x014
13 #define OHCI1394_ConfigROMhdr 0x018
14 #define OHCI1394_BusID 0x01C
15 #define OHCI1394_BusOptions 0x020
16 #define OHCI1394_GUIDHi 0x024
[all …]
/Linux-v6.1/sound/pci/ice1712/
Dwm8766.h13 #define WM8766_REG_DACL1 0x00
14 #define WM8766_REG_DACR1 0x01
15 #define WM8766_VOL_MASK 0x1ff /* incl. update bit */
17 #define WM8766_REG_DACCTRL1 0x02
18 #define WM8766_DAC_MUTEALL (1 << 0)
23 #define WM8766_DAC_PL_MASK 0x1e0
30 #define WM8766_REG_IFCTRL 0x03
31 #define WM8766_IF_FMT_RIGHTJ (0 << 0)
32 #define WM8766_IF_FMT_LEFTJ (1 << 0)
33 #define WM8766_IF_FMT_I2S (2 << 0)
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dqcom,qmp-ufs-phy.yaml68 "^phy@[0-9a-f]+$":
77 const: 0
168 "^phy@[0-9a-f]+$":
186 "^phy@[0-9a-f]+$":
204 "^phy@[0-9a-f]+$":
218 reg = <0x01d87000 0xe10>;
221 ranges = <0x0 0x01d87000 0x1000>;
226 resets = <&ufs_mem_hc 0>;
233 reg = <0x400 0x108>,
234 <0x600 0x1e0>,
[all …]
/Linux-v6.1/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcs-v4_20.h10 #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
11 #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
12 #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
13 #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
Dphy-qcom-qmp-pcs-ufs-v5.h11 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
12 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
13 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
14 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
15 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
16 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
17 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
18 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
19 #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
20 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
[all …]
Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
11 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
12 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
13 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
14 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
15 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
16 #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
17 #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
18 #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
19 #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
[all …]
Dphy-qcom-qmp-pcs-ufs-v4.h10 #define QPHY_V4_PCS_UFS_PHY_START 0x000
11 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V4_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
16 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
Dphy-qcom-qmp-pcs-v2.h10 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
11 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
12 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
13 #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
14 #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
15 #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
16 #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
17 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
18 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
19 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
[all …]
Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-driver-jz4780-efuse10 0x000 64 bit Random Number
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
13 0x028 3520 bit Reserved
14 0x1E0 8 bit Protect Segment
15 0x1E1 2296 bit HDMI Key
16 0x300 2048 bit Security boot key
/Linux-v6.1/drivers/usb/host/
Dbcma-hcd.c38 #define USB_BCMA_CLKCTLST_USB_CLK_REQ 0x00000100
56 for (i = 0; i < timeout; i++) { in bcma_wait_bits()
59 return 0; in bcma_wait_bits()
70 if (dev->bus->chipinfo.id == 0x4716) { in bcma_hcd_4716wa()
75 tmp = 0x1846b; /* set CDR to 0x11(fast) */ in bcma_hcd_4716wa()
77 tmp = 0x1046b; /* set CDR to 0x10(slow) */ in bcma_hcd_4716wa()
79 tmp = 0; in bcma_hcd_4716wa()
85 bcma_write32(dev, 0x524, 0x1); /* write sel to enable */ in bcma_hcd_4716wa()
88 bcma_write32(dev, 0x524, tmp); in bcma_hcd_4716wa()
90 bcma_write32(dev, 0x524, 0x4ab); in bcma_hcd_4716wa()
[all …]
/Linux-v6.1/arch/sh/drivers/pci/
Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dti,iodelay.txt24 reg = <0x4844a000 0x0d1c>;
26 #size-cells = <0>;
35 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
36 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
37 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
38 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
40 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
41 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
42 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-14nm.yaml52 reg = <0x0ae94400 0x200>,
53 <0x0ae94600 0x280>,
54 <0x0ae94a00 0x1e0>;
60 #phy-cells = <0>;
Ddsi-phy-10nm.yaml83 reg = <0x0ae94400 0x200>,
84 <0x0ae94600 0x280>,
85 <0x0ae94a00 0x1e0>;
91 #phy-cells = <0>;
98 qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
99 qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
/Linux-v6.1/sound/isa/sb/
Demu8000_patch.c29 for (i = 0; i < EMU8000_DRAM_VOICES; i++) { in snd_emu8000_open_dma()
35 EMU8000_VTFT_WRITE(emu, 30, 0); in snd_emu8000_open_dma()
36 EMU8000_PSST_WRITE(emu, 30, 0x1d8); in snd_emu8000_open_dma()
37 EMU8000_CSL_WRITE(emu, 30, 0x1e0); in snd_emu8000_open_dma()
38 EMU8000_CCCA_WRITE(emu, 30, 0x1d8); in snd_emu8000_open_dma()
39 EMU8000_VTFT_WRITE(emu, 31, 0); in snd_emu8000_open_dma()
40 EMU8000_PSST_WRITE(emu, 31, 0x1d8); in snd_emu8000_open_dma()
41 EMU8000_CSL_WRITE(emu, 31, 0x1e0); in snd_emu8000_open_dma()
42 EMU8000_CCCA_WRITE(emu, 31, 0x1d8); in snd_emu8000_open_dma()
44 return 0; in snd_emu8000_open_dma()
[all …]
/Linux-v6.1/arch/arm/mach-tegra/
Dirq.c26 #define SGI_MASK 0xFFFF
51 writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); in tegra_gic_notifier()
/Linux-v6.1/drivers/media/platform/chips-media/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mm-phycore-som.dtsi21 reg = <0x0 0x40000000 0 0x80000000>;
76 pinctrl-0 = <&pinctrl_fec1>;
81 #size-cells = <0>;
83 ethphy0: ethernet-phy@0 {
90 reg = <0>;
101 pinctrl-0 = <&pinctrl_flexspi0>;
104 som_flash: flash@0 {
106 reg = <0>;
123 pinctrl-0 = <&pinctrl_i2c1>;
131 reg = <0x08>;
[all …]
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt7601u/
Deeprom.h12 #define MT7601U_EE_MAX_VER 0x0d
18 MT_EE_CHIP_ID = 0x00,
19 MT_EE_VERSION_FAE = 0x02,
20 MT_EE_VERSION_EE = 0x03,
21 MT_EE_MAC_ADDR = 0x04,
22 MT_EE_NIC_CONF_0 = 0x34,
23 MT_EE_NIC_CONF_1 = 0x36,
24 MT_EE_COUNTRY_REGION = 0x39,
25 MT_EE_FREQ_OFFSET = 0x3a,
26 MT_EE_NIC_CONF_2 = 0x42,
[all …]

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