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/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mm-mx8menlo.dts21 pinctrl-0 = <&pinctrl_led>;
39 pinctrl-0 = <&pinctrl_beeper>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 pinctrl-0 = <&pinctrl_ecspi1>;
60 canfd: can@0 {
65 reg = <0>;
72 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
76 spidev@0 {
78 reg = <0>;
[all …]
Dimx8mp-verdin.dtsi24 brightness-levels = <0 45 63 88 119 158 203 255>;
29 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
32 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
38 brightness-levels = <0 45 63 88 119 158 203 255>;
43 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
50 pinctrl-0 = <&pinctrl_gpio_keys>;
55 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
91 pinctrl-0 = <&pinctrl_reg_eth>;
107 pinctrl-0 = <&pinctrl_usb1_vbus>;
119 pinctrl-0 = <&pinctrl_usb2_vbus>;
[all …]
Dimx8mp-msc-sm2s.dtsi25 pinctrl-0 = <&pinctrl_usb0_vbus>;
36 pinctrl-0 = <&pinctrl_usb1_vbus>;
46 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
70 lcd0_backlight: backlight-0 {
73 pinctrl-0 = <&pinctrl_lcd0_backlight>;
74 pwms = <&pwm1 0 100000 0>;
75 brightness-levels = <0 255>;
85 pinctrl-0 = <&pinctrl_lcd1_backlight>;
86 pwms = <&pwm2 0 100000 0>;
87 brightness-levels = <0 255>;
[all …]
Dimx8mm-emcon.dtsi19 pinctrl-0 = <&pinctrl_gpio_led>;
38 pwms = <&pwm1 0 50000 0>;
40 0 4 8 16 32 64 80 96 112
68 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
76 pinctrl-0 = <&pinctrl_fec1>;
84 #size-cells = <0>;
86 ethphy0: ethernet-phy@0 {
88 reg = <0>;
97 pinctrl-0 = <&pinctrl_flexspi0>;
101 flash0: flash@0 {
[all …]
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dimx53-m53menlo.dts15 pinctrl-0 = <&pinctrl_power_button>;
27 pinctrl-0 = <&pinctrl_power_out>;
35 pinctrl-0 = <&pinctrl_led>;
61 #size-cells = <0>;
63 port@0 {
64 reg = <0>;
83 pinctrl-0 = <&pinctrl_display_gpio>;
85 enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
96 pinctrl-0 = <&pinctrl_beeper>;
105 gpio = <&gpio1 2 0>;
[all …]
Dimx53-smd.dts16 reg = <0x70000000 0x40000000>;
24 gpios = <&gpio2 14 0>;
30 gpios = <&gpio2 15 0>;
38 pinctrl-0 = <&pinctrl_esdhc1>;
46 pinctrl-0 = <&pinctrl_esdhc2>;
53 pinctrl-0 = <&pinctrl_uart3>;
60 pinctrl-0 = <&pinctrl_ecspi1>;
64 zigbee: mc1323@0 {
67 reg = <0>;
77 partition@0 {
[all …]
Dimx53-cx9020.dts20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
24 display-0 {
26 #size-cells = <0>;
30 pinctrl-0 = <&pinctrl_ipu_disp0>;
32 port@0 {
33 reg = <0>;
66 #size-cells = <0>;
68 port@0 {
69 reg = <0>;
[all …]
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
Ddra72x-mmc-iodelay.dtsi37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt7986-topckgen.c178 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
180 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
182 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
184 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
187 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
189 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
190 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
/Linux-v6.1/drivers/media/platform/chips-media/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/falcon/
Dv1.c38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); in nvkm_falcon_v1_load_imem()
40 for (i = 0; i < size / 4; i++) { in nvkm_falcon_v1_load_imem()
42 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); in nvkm_falcon_v1_load_imem()
55 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
56 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
57 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), in nvkm_falcon_v1_load_imem()
62 /* code must be padded to 0x40 words */ in nvkm_falcon_v1_load_imem()
[all …]
/Linux-v6.1/drivers/gpu/drm/armada/
Darmada_debugfs.c29 return 0; in armada_debugfs_gem_linear_show()
37 for (i = 0x84; i <= 0x1c4; i += 4) { in armada_debugfs_crtc_reg_show()
39 seq_printf(m, "0x%04x: 0x%08x\n", i, v); in armada_debugfs_crtc_reg_show()
42 return 0; in armada_debugfs_crtc_reg_show()
60 if (*off != 0) in armada_debugfs_crtc_reg_write()
61 return 0; in armada_debugfs_crtc_reg_write()
67 if (ret < 0) in armada_debugfs_crtc_reg_write()
69 buf[len] = '\0'; in armada_debugfs_crtc_reg_write()
73 if (reg < 0x84 || reg > 0x1c4 || reg & 3) in armada_debugfs_crtc_reg_write()
101 { "gem_linear", armada_debugfs_gem_linear_show, 0 },
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcs-ufs-v3.h9 #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
10 #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
11 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
12 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
13 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
14 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
15 #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
16 #define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4
Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
11 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
12 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
13 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
14 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
15 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
16 #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
17 #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
18 #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
19 #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
[all …]
Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
Dphy-qcom-qmp-pcs-v4.h10 #define QPHY_V4_PCS_SW_RESET 0x000
11 #define QPHY_V4_PCS_REVISION_ID0 0x004
12 #define QPHY_V4_PCS_REVISION_ID1 0x008
13 #define QPHY_V4_PCS_REVISION_ID2 0x00c
14 #define QPHY_V4_PCS_REVISION_ID3 0x010
15 #define QPHY_V4_PCS_PCS_STATUS1 0x014
16 #define QPHY_V4_PCS_PCS_STATUS2 0x018
17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
18 #define QPHY_V4_PCS_PCS_STATUS4 0x020
19 #define QPHY_V4_PCS_PCS_STATUS5 0x024
[all …]
/Linux-v6.1/arch/arm/mach-s3c/
Dregs-gpio-memport-s3c64xx.h14 #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15 #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
17 #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18 #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19 #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
21 #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22 #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
/Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define INTR2_CLEAR 0x02c
20 #define HIST_INTR_EN 0x01c
21 #define HIST_INTR_STATUS 0x020
22 #define HIST_INTR_CLEAR 0x024
[all …]
/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_lrc.c29 #define POSTED BIT(0) in set_offsets()
30 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
32 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
33 (((x) >> 2) & 0x7f) in set_offsets()
34 #define END 0 in set_offsets()
47 count = *data & 0x3f; in set_offsets()
60 u32 offset = 0; in set_offsets()
69 regs[0] = base + (offset << 2); in set_offsets()
78 *regs |= BIT(0); in set_offsets()
84 LRI(11, 0),
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dqcom,hdmi-phy-qmp.yaml51 const: 0
54 const: 0
70 reg = <0x009a0600 0x1c4>,
71 <0x009a0a00 0x124>,
72 <0x009a0c00 0x124>,
73 <0x009a0e00 0x124>,
74 <0x009a1000 0x124>,
75 <0x009a1200 0x0c8>;
89 #clock-cells = <0>;
90 #phy-cells = <0>;
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dipq8074.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
32 #address-cells = <0x1>;
33 #size-cells = <0x0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
69 cache-level = <0x2>;
[all …]
/Linux-v6.1/drivers/pinctrl/
Dpinctrl-pic32.h12 #define ANSEL_REG 0x00
13 #define TRIS_REG 0x10
14 #define PORT_REG 0x20
15 #define LAT_REG 0x30
16 #define ODCU_REG 0x40
17 #define CNPU_REG 0x50
18 #define CNPD_REG 0x60
19 #define CNCON_REG 0x70
20 #define CNEN_REG 0x80
21 #define CNSTAT_REG 0x90
[all …]

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