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/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt7986-topckgen.c178 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
180 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
182 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
184 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
187 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
189 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
190 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mp-tqma8mpql-mba8mpxl.dts24 io-channels = <&adc 0>, <&adc 1>;
42 pinctrl-0 = <&pinctrl_backlight>;
43 pwms = <&pwm2 0 5000000 0>;
44 brightness-levels = <0 4 8 16 32 64 128 255>;
54 pinctrl-0 = <&pinctrl_gpiobutton>;
73 pinctrl-0 = <&pinctrl_gpioled>;
75 led-0 {
78 function-enumerator = <0>;
104 pinctrl-0 = <&pinctrl_lvdsdisplay>;
114 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
[all …]
/Linux-v6.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/Linux-v6.1/drivers/net/phy/
Dnational.c23 #define DP83865_PHY_ID 0x20005c7a
25 #define DP83865_INT_STATUS 0x14
26 #define DP83865_INT_MASK 0x15
27 #define DP83865_INT_CLEAR 0x17
29 #define DP83865_INT_REMOTE_FAULT 0x0008
30 #define DP83865_INT_ANE_COMPLETED 0x0010
31 #define DP83865_INT_LINK_CHANGE 0xe000
37 #define NS_EXP_MEM_CTL 0x16
38 #define NS_EXP_MEM_DATA 0x1d
39 #define NS_EXP_MEM_ADD 0x1e
[all …]
/Linux-v6.1/drivers/soc/renesas/
Dr8a7742-sysc.c15 { "always-on", 0, 0, R8A7742_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca15-scu", 0x180, 0, R8A7742_PD_CA15_SCU, R8A7742_PD_ALWAYS_ON,
18 { "ca15-cpu0", 0x40, 0, R8A7742_PD_CA15_CPU0, R8A7742_PD_CA15_SCU,
20 { "ca15-cpu1", 0x40, 1, R8A7742_PD_CA15_CPU1, R8A7742_PD_CA15_SCU,
22 { "ca15-cpu2", 0x40, 2, R8A7742_PD_CA15_CPU2, R8A7742_PD_CA15_SCU,
24 { "ca15-cpu3", 0x40, 3, R8A7742_PD_CA15_CPU3, R8A7742_PD_CA15_SCU,
26 { "ca7-scu", 0x100, 0, R8A7742_PD_CA7_SCU, R8A7742_PD_ALWAYS_ON,
28 { "ca7-cpu0", 0x1c0, 0, R8A7742_PD_CA7_CPU0, R8A7742_PD_CA7_SCU,
30 { "ca7-cpu1", 0x1c0, 1, R8A7742_PD_CA7_CPU1, R8A7742_PD_CA7_SCU,
32 { "ca7-cpu2", 0x1c0, 2, R8A7742_PD_CA7_CPU2, R8A7742_PD_CA7_SCU,
[all …]
Dr8a7790-sysc.c15 { "always-on", 0, 0, R8A7790_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca15-scu", 0x180, 0, R8A7790_PD_CA15_SCU, R8A7790_PD_ALWAYS_ON,
18 { "ca15-cpu0", 0x40, 0, R8A7790_PD_CA15_CPU0, R8A7790_PD_CA15_SCU,
20 { "ca15-cpu1", 0x40, 1, R8A7790_PD_CA15_CPU1, R8A7790_PD_CA15_SCU,
22 { "ca15-cpu2", 0x40, 2, R8A7790_PD_CA15_CPU2, R8A7790_PD_CA15_SCU,
24 { "ca15-cpu3", 0x40, 3, R8A7790_PD_CA15_CPU3, R8A7790_PD_CA15_SCU,
26 { "ca7-scu", 0x100, 0, R8A7790_PD_CA7_SCU, R8A7790_PD_ALWAYS_ON,
28 { "ca7-cpu0", 0x1c0, 0, R8A7790_PD_CA7_CPU0, R8A7790_PD_CA7_SCU,
30 { "ca7-cpu1", 0x1c0, 1, R8A7790_PD_CA7_CPU1, R8A7790_PD_CA7_SCU,
32 { "ca7-cpu2", 0x1c0, 2, R8A7790_PD_CA7_CPU2, R8A7790_PD_CA7_SCU,
[all …]
Dr8a7745-sysc.c15 { "always-on", 0, 0, R8A7745_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca7-scu", 0x100, 0, R8A7745_PD_CA7_SCU, R8A7745_PD_ALWAYS_ON,
18 { "ca7-cpu0", 0x1c0, 0, R8A7745_PD_CA7_CPU0, R8A7745_PD_CA7_SCU,
20 { "ca7-cpu1", 0x1c0, 1, R8A7745_PD_CA7_CPU1, R8A7745_PD_CA7_SCU,
22 { "sgx", 0xc0, 0, R8A7745_PD_SGX, R8A7745_PD_ALWAYS_ON },
Dr8a77470-sysc.c15 { "always-on", 0, 0, R8A77470_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca7-scu", 0x100, 0, R8A77470_PD_CA7_SCU, R8A77470_PD_ALWAYS_ON,
18 { "ca7-cpu0", 0x1c0, 0, R8A77470_PD_CA7_CPU0, R8A77470_PD_CA7_SCU,
20 { "ca7-cpu1", 0x1c0, 1, R8A77470_PD_CA7_CPU1, R8A77470_PD_CA7_SCU,
22 { "sgx", 0xc0, 0, R8A77470_PD_SGX, R8A77470_PD_ALWAYS_ON },
Dr8a7794-sysc.c15 { "always-on", 0, 0, R8A7794_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca7-scu", 0x100, 0, R8A7794_PD_CA7_SCU, R8A7794_PD_ALWAYS_ON,
18 { "ca7-cpu0", 0x1c0, 0, R8A7794_PD_CA7_CPU0, R8A7794_PD_CA7_SCU,
20 { "ca7-cpu1", 0x1c0, 1, R8A7794_PD_CA7_CPU1, R8A7794_PD_CA7_SCU,
22 { "sh-4a", 0x80, 0, R8A7794_PD_SH_4A, R8A7794_PD_ALWAYS_ON },
23 { "sgx", 0xc0, 0, R8A7794_PD_SGX, R8A7794_PD_ALWAYS_ON },
Dr8a77965-sysc.c18 { "always-on", 0, 0, R8A77965_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
19 { "ca57-scu", 0x1c0, 0, R8A77965_PD_CA57_SCU, R8A77965_PD_ALWAYS_ON,
21 { "ca57-cpu0", 0x80, 0, R8A77965_PD_CA57_CPU0, R8A77965_PD_CA57_SCU,
23 { "ca57-cpu1", 0x80, 1, R8A77965_PD_CA57_CPU1, R8A77965_PD_CA57_SCU,
25 { "cr7", 0x240, 0, R8A77965_PD_CR7, R8A77965_PD_ALWAYS_ON },
26 { "a3vc", 0x380, 0, R8A77965_PD_A3VC, R8A77965_PD_ALWAYS_ON },
27 { "a3vp", 0x340, 0, R8A77965_PD_A3VP, R8A77965_PD_ALWAYS_ON },
28 { "a2vc1", 0x3c0, 1, R8A77965_PD_A2VC1, R8A77965_PD_A3VC },
29 { "3dg-a", 0x100, 0, R8A77965_PD_3DG_A, R8A77965_PD_ALWAYS_ON },
30 { "3dg-b", 0x100, 1, R8A77965_PD_3DG_B, R8A77965_PD_3DG_A },
[all …]
Dr8a774b1-sysc.c18 { "always-on", 0, 0, R8A774B1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
19 { "ca57-scu", 0x1c0, 0, R8A774B1_PD_CA57_SCU, R8A774B1_PD_ALWAYS_ON,
21 { "ca57-cpu0", 0x80, 0, R8A774B1_PD_CA57_CPU0, R8A774B1_PD_CA57_SCU,
23 { "ca57-cpu1", 0x80, 1, R8A774B1_PD_CA57_CPU1, R8A774B1_PD_CA57_SCU,
25 { "a3vc", 0x380, 0, R8A774B1_PD_A3VC, R8A774B1_PD_ALWAYS_ON },
26 { "a3vp", 0x340, 0, R8A774B1_PD_A3VP, R8A774B1_PD_ALWAYS_ON },
27 { "a2vc1", 0x3c0, 1, R8A774B1_PD_A2VC1, R8A774B1_PD_A3VC },
28 { "3dg-a", 0x100, 0, R8A774B1_PD_3DG_A, R8A774B1_PD_ALWAYS_ON },
29 { "3dg-b", 0x100, 1, R8A774B1_PD_3DG_B, R8A774B1_PD_3DG_A },
35 .extmask_offs = 0x2f8,
[all …]
/Linux-v6.1/sound/pci/oxygen/
Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
Dwm8785.h5 #define WM8785_R0 0
11 #define WM8785_MCR_MASK 0x007
12 #define WM8785_MCR_SLAVE 0x000
13 #define WM8785_MCR_MASTER_128 0x001
14 #define WM8785_MCR_MASTER_192 0x002
15 #define WM8785_MCR_MASTER_256 0x003
16 #define WM8785_MCR_MASTER_384 0x004
17 #define WM8785_MCR_MASTER_512 0x005
18 #define WM8785_MCR_MASTER_768 0x006
19 #define WM8785_OSR_MASK 0x018
[all …]
/Linux-v6.1/drivers/media/platform/chips-media/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-com.h10 #define QSERDES_COM_ATB_SEL1 0x000
11 #define QSERDES_COM_ATB_SEL2 0x004
12 #define QSERDES_COM_FREQ_UPDATE 0x008
13 #define QSERDES_COM_BG_TIMER 0x00c
14 #define QSERDES_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_COM_SSC_PER1 0x01c
18 #define QSERDES_COM_SSC_PER2 0x020
19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
[all …]
Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
11 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
12 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
13 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
14 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
15 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
16 #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
17 #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
18 #define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
19 #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
16 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
17 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
18 #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
19 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
20 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
21 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
[all …]
/Linux-v6.1/drivers/firewire/
Dohci.h7 #define OHCI1394_Version 0x000
8 #define OHCI1394_GUID_ROM 0x004
9 #define OHCI1394_ATRetries 0x008
10 #define OHCI1394_CSRData 0x00C
11 #define OHCI1394_CSRCompareData 0x010
12 #define OHCI1394_CSRControl 0x014
13 #define OHCI1394_ConfigROMhdr 0x018
14 #define OHCI1394_BusID 0x01C
15 #define OHCI1394_BusOptions 0x020
16 #define OHCI1394_GUIDHi 0x024
[all …]
/Linux-v6.1/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/Linux-v6.1/arch/arm/mach-s3c/
Dregs-gpio-memport-s3c64xx.h14 #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15 #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
17 #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18 #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19 #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
21 #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22 #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
/Linux-v6.1/include/uapi/linux/
Dadfs_fs.h9 * Disc Record at disc address 0xc00
40 #define ADFS_DISCRECORD (0xc00)
41 #define ADFS_DR_OFFSET (0x1c0)
/Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define INTR2_CLEAR 0x02c
20 #define HIST_INTR_EN 0x01c
21 #define HIST_INTR_STATUS 0x020
22 #define HIST_INTR_CLEAR 0x024
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dimx25-eukrea-cpuimx25.dtsi14 reg = <0x80000000 0x4000000>; /* 64M */
21 pinctrl-0 = <&pinctrl_fec>;
27 pinctrl-0 = <&pinctrl_i2c1>;
32 reg = <0x51>;
40 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
41 MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
42 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
43 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
44 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
45 MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/sound/
Damlogic,axg-fifo.txt19 - #sound-dai-cells: must be 0.
28 reg = <0x0 0x1c0 0x0 0x1c>;
29 #sound-dai-cells = <0>;
/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_lrc.c29 #define POSTED BIT(0) in set_offsets()
30 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
32 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
33 (((x) >> 2) & 0x7f) in set_offsets()
34 #define END 0 in set_offsets()
47 count = *data & 0x3f; in set_offsets()
60 u32 offset = 0; in set_offsets()
69 regs[0] = base + (offset << 2); in set_offsets()
78 *regs |= BIT(0); in set_offsets()
84 LRI(11, 0),
[all …]

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