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/Linux-v6.1/drivers/media/platform/chips-media/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dhisilicon-histb-pcie.txt38 - phys: List of phandle and phy mode specifier, should be 0.
44 reg = <0xf9860000 0x1000>,
45 <0xf0000000 0x2000>,
46 <0xf2000000 0x01000000>;
51 bus-range = <0 15>;
53 ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
54 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
58 interrupt-map-mask = <0 0 0 0>;
59 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
/Linux-v6.1/drivers/clk/hisilicon/
Dcrg-hi3798cv200.c45 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
46 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
47 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_doorbell.h88 AMDGPU_DOORBELL_KIQ = 0x000,
89 AMDGPU_DOORBELL_HIQ = 0x001,
90 AMDGPU_DOORBELL_DIQ = 0x002,
91 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
92 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
93 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
94 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
95 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
96 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
97 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
[all …]
/Linux-v6.1/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
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/Linux-v6.1/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
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/Linux-v6.1/drivers/clk/sunxi-ng/
Dccu-sun50i-a100-r.c23 { .index = 3, .shift = 0, .width = 5 },
38 .reg = 0x000,
43 0),
47 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
50 .div = _SUNXI_CCU_DIV(0, 2),
53 .reg = 0x00c,
57 0),
73 .reg = 0x010,
78 0),
91 0x11c, BIT(0), 0);
[all …]
Dccu-sun50i-h6-r.c29 { .index = 3, .shift = 0, .width = 5 },
44 .reg = 0x000,
49 0),
53 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
55 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
69 .reg = 0x010,
74 0),
86 0x11c, BIT(0), 0);
88 0x12c, BIT(0), 0);
90 0x13c, BIT(0), 0);
[all …]
/Linux-v6.1/include/dt-bindings/clock/
Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
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/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
16 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
17 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
18 #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
19 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
20 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
21 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
[all …]
Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_PER1 0x01c
12 #define QSERDES_PLL_SSC_PER2 0x020
13 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
14 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
15 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
17 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
18 #define QSERDES_PLL_CLK_ENABLE1 0x040
19 #define QSERDES_PLL_SYS_CLK_CTRL 0x044
[all …]
Dphy-qcom-qmp-qserdes-com-v5.h10 #define QSERDES_V5_COM_ATB_SEL1 0x000
11 #define QSERDES_V5_COM_ATB_SEL2 0x004
12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V5_COM_BG_TIMER 0x00c
14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V5_COM_SSC_PER1 0x01c
18 #define QSERDES_V5_COM_SSC_PER2 0x020
19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
Dphy-qcom-qmp-qserdes-com-v4.h10 #define QSERDES_V4_COM_ATB_SEL1 0x000
11 #define QSERDES_V4_COM_ATB_SEL2 0x004
12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V4_COM_BG_TIMER 0x00c
14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V4_COM_SSC_PER1 0x01c
18 #define QSERDES_V4_COM_SSC_PER2 0x020
19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
Dphy-qcom-qmp-qserdes-com.h10 #define QSERDES_COM_ATB_SEL1 0x000
11 #define QSERDES_COM_ATB_SEL2 0x004
12 #define QSERDES_COM_FREQ_UPDATE 0x008
13 #define QSERDES_COM_BG_TIMER 0x00c
14 #define QSERDES_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_COM_SSC_PER1 0x01c
18 #define QSERDES_COM_SSC_PER2 0x020
19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
[all …]
Dphy-qcom-qmp-pcs-v4.h10 #define QPHY_V4_PCS_SW_RESET 0x000
11 #define QPHY_V4_PCS_REVISION_ID0 0x004
12 #define QPHY_V4_PCS_REVISION_ID1 0x008
13 #define QPHY_V4_PCS_REVISION_ID2 0x00c
14 #define QPHY_V4_PCS_REVISION_ID3 0x010
15 #define QPHY_V4_PCS_PCS_STATUS1 0x014
16 #define QPHY_V4_PCS_PCS_STATUS2 0x018
17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
18 #define QPHY_V4_PCS_PCS_STATUS4 0x020
19 #define QPHY_V4_PCS_PCS_STATUS5 0x024
[all …]
/Linux-v6.1/sound/soc/meson/
Daiu.h18 PCLK = 0,
63 #define AIU_IEC958_BPF 0x000
64 #define AIU_958_MISC 0x010
65 #define AIU_IEC958_DCU_FF_CTRL 0x01c
66 #define AIU_958_CHSTAT_L0 0x020
67 #define AIU_958_CHSTAT_L1 0x024
68 #define AIU_958_CTRL 0x028
69 #define AIU_I2S_SOURCE_DESC 0x034
70 #define AIU_I2S_DAC_CFG 0x040
71 #define AIU_I2S_SYNC 0x044
[all …]
/Linux-v6.1/arch/xtensa/include/asm/
Dmxregs.h20 * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p
21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
22 * 0180 0...0m..m Clear enable specified by mask (m)
23 * 0184 0...0m..m Set enable specified by mask (m)
24 * 0190 0...0x..x 8-bit IPI partition register
30 * 0200 0...0m..m RunStall core 'n'
34 #define MIROUT(irq) (0x000 + (irq))
35 #define MIPICAUSE(cpu) (0x100 + (cpu))
36 #define MIPISET(cause) (0x140 + (cause))
37 #define MIENG 0x180
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dti,iodelay.txt24 reg = <0x4844a000 0x0d1c>;
26 #size-cells = <0>;
35 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
36 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
37 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
38 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
40 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
41 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
42 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/Linux-v6.1/arch/powerpc/include/asm/
Dtsi108.h18 #define TSI108_REG_SIZE (0x10000)
21 #define TSI108_HLP_SIZE 0x1000
22 #define TSI108_PCI_SIZE 0x1000
23 #define TSI108_CLK_SIZE 0x1000
24 #define TSI108_PB_SIZE 0x1000
25 #define TSI108_SD_SIZE 0x1000
26 #define TSI108_DMA_SIZE 0x1000
27 #define TSI108_ETH_SIZE 0x1000
28 #define TSI108_I2C_SIZE 0x400
29 #define TSI108_MPIC_SIZE 0x400
[all …]

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