Searched +full:0 +full:x18013000 (Results 1 – 5 of 5) sorted by relevance
127 reg = <0x18012000 0x1000>;130 interrupt-map-mask = <0 0 0 0>;131 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;133 linux,pci-domain = <0>;135 bus-range = <0x00 0xff>;140 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,141 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;143 phys = <&phy 0 5>;147 brcm,pcie-ob-axi-offset = <0x00000000>;165 reg = <0x18013000 0x1000>;[all …]
45 #size-cells = <0>;47 cpu0: cpu@0 {51 reg = <0x0>;64 ranges = <0x00000000 0x19000000 0x00023000>;68 a9pll: arm_clk@0 {69 #clock-cells = <0>;72 reg = <0x0 0x1000>;77 reg = <0x20200 0x100>;84 reg = <0x20600 0x20>;92 reg = <0x20620 0x20>;[all …]
48 memory@0 {50 reg = <0 0>;55 #size-cells = <0>;57 cpu@0 {61 reg = <0x0>;74 ranges = <0x00000000 0x19000000 0x1000000>;80 reg = <0x20200 0x100>;88 #address-cells = <0>;90 reg = <0x21000 0x1000>,91 <0x20100 0x100>;[all …]
54 #size-cells = <0>;56 cpu0: cpu@0 {60 reg = <0x0>;68 secondary-boot-reg = <0xffff0fec>;69 reg = <0x1>;82 ranges = <0x00000000 0x19000000 0x00023000>;86 a9pll: arm_clk@0 {87 #clock-cells = <0>;90 reg = <0x00000 0x1000>;95 reg = <0x20200 0x100>;[all …]
111 #define MT_MCU_WFDMA0_BASE 0x2000114 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)117 #define MT_MCU_WFDMA1_BASE 0x3000121 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)127 #define MT_PLE_BASE 0x820c0000132 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)133 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)143 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))145 #define MT_PSE_BASE 0x820c8000149 #define MT_MDP_BASE 0x820cd000[all …]
