/Linux-v6.6/arch/arm/boot/dts/nxp/imx/ |
D | imx6ull-jozacp.dts | 25 led-0 { 28 function-enumerator = <0>; 29 pwms = <&pwm1 0 10000000 0>; 37 pwms = <&pwm3 0 10000000 0>; 45 pwms = <&pwm5 0 10000000 0>; 59 pwms = <&pwm2 0 10000000 0>; 67 pwms = <&pwm4 0 10000000 0>; 75 pwms = <&pwm6 0 10000000 0>; 98 pinctrl-0 = <&pinctrl_vbus>; 110 pinctrl-0 = <&pinctrl_wifi_npd>; [all …]
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D | imx6sl-tolino-vision.dts | 29 pwms = <&ec 0 50000>; 36 pinctrl-0 = <&pinctrl_backlight_power>; 49 pinctrl-0 = <&pinctrl_gpio_keys>; 77 pinctrl-0 = <&pinctrl_leds>; 79 led-0 { 97 reg = <0x80000000 0x20000000>; 103 pinctrl-0 = <&pinctrl_wifi_power>; 114 pinctrl-0 = <&pinctrl_wifi_reset>; 116 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 122 pinctrl-0 = <&pinctrl_i2c1>; [all …]
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/Linux-v6.6/arch/m68k/include/asm/ |
D | apollohw.h | 52 #define IO_BASE 0x80000000 62 #define SAU7_SIO01_PHYSADDR 0x10400 63 #define SAU7_SIO23_PHYSADDR 0x10500 64 #define SAU7_RTC_PHYSADDR 0x10900 65 #define SAU7_PICA 0x11000 66 #define SAU7_PICB 0x11100 67 #define SAU7_CPUCTRL 0x10100 68 #define SAU7_TIMER 0x010800 70 #define SAU8_SIO01_PHYSADDR 0x8400 71 #define SAU8_RTC_PHYSADDR 0x8900 [all …]
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/Linux-v6.6/Documentation/devicetree/bindings/pinctrl/ |
D | nvidia,tegra234-pinmux.yaml | 123 reg = <0x2430000 0x17000>; 126 pinctrl-0 = <&pex_rst_c5_out_state>;
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D | nvidia,tegra194-pinmux.yaml | 266 reg = <0x2430000 0x17000>; 269 pinctrl-0 = <&pex_rst_c5_out_state>;
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/Linux-v6.6/arch/arc/boot/dts/ |
D | vdk_axs10x_mb.dtsi | 13 ranges = <0x00000000 0xe0000000 0x10000000>; 20 #clock-cells = <0>; 26 #clock-cells = <0>; 30 #clock-cells = <0>; 39 reg = < 0x18000 0x2000 >; 43 snps,phy-addr = < 0 >; // VDK model phy address is 0 51 reg = < 0x40000 0x100 >; 57 reg = <0x20000 0x100>; 67 reg = <0x21000 0x100>; 77 reg = <0x22000 0x100>; [all …]
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D | axs10x_mb.dtsi | 17 ranges = <0x00000000 0x0 0xe0000000 0x10000000>; 23 reg = <0x11220 0x4>; 28 reg = <0x100a0 0x10>; 30 #clock-cells = <0>; 37 #clock-cells = <0>; 43 #clock-cells = <0>; 49 #clock-cells = <0>; 62 #clock-cells = <0>; 68 reg = <0x10080 0x10>, <0x110 0x10>; 69 #clock-cells = <0>; [all …]
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/Linux-v6.6/arch/arm/mach-imx/ |
D | mx2x.h | 16 #define MX2x_AIPI_BASE_ADDR 0x10000000 18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) 19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) 20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000) 21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000) 22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000) 23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000) 24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000) 25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000) 26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000) [all …]
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/Linux-v6.6/arch/powerpc/boot/dts/fsl/ |
D | interlaken-lac-portals.dtsi | 34 #address-cells = <0x1>; 35 #size-cells = <0x1>; 38 lportal0: lac-portal@0 { 39 compatible = "fsl,interlaken-lac-portal-v1.0"; 40 reg = <0x0 0x1000>; 44 compatible = "fsl,interlaken-lac-portal-v1.0"; 45 reg = <0x1000 0x1000>; 49 compatible = "fsl,interlaken-lac-portal-v1.0"; 50 reg = <0x2000 0x1000>; 54 compatible = "fsl,interlaken-lac-portal-v1.0"; [all …]
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/Linux-v6.6/drivers/soc/tegra/cbb/ |
D | tegra234-cbb.c | 8 * Error types supported by CBB2.0 are: 27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0 28 #define FABRIC_EN_CFG_STATUS_0_0 0x40 29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60 30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80 31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84 33 #define FABRIC_MN_MASTER_ERR_EN_0 0x200 34 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204 35 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208 36 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c [all …]
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/Linux-v6.6/arch/arm/boot/dts/ti/omap/ |
D | dra74x.dtsi | 49 reg = <0x41500000 0x100>; 55 reg = <0x41501000 0x4>, 56 <0x41501010 0x4>, 57 <0x41501014 0x4>; 65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; 69 ranges = <0x0 0x41501000 0x1000>; 73 mmu0_dsp2: mmu@0 { 75 reg = <0x0 0x100>; 77 #iommu-cells = <0>; 78 ti,syscon-mmuconfig = <&dsp2_system 0x0>; [all …]
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/Linux-v6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
D | dpu_7_2_sc7280.h | 12 .max_mixer_blendstages = 0x7, 22 .base = 0x0, .len = 0x2014, 24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, 35 .base = 0x15000, .len = 0x1e8, 40 .base = 0x16000, .len = 0x1e8, 45 .base = 0x17000, .len = 0x1e8, [all …]
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D | dpu_7_0_sm8350.h | 12 .max_mixer_blendstages = 0xb, 24 .base = 0x0, .len = 0x494, 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, [all …]
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D | dpu_9_0_sm8550.h | 12 .max_mixer_blendstages = 0xb, 24 .base = 0, .len = 0x494, 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, [all …]
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D | dpu_8_1_sm8450.h | 12 .max_mixer_blendstages = 0xb, 24 .base = 0x0, .len = 0x494, 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, [all …]
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D | dpu_8_0_sc8280xp.h | 24 .base = 0x0, .len = 0x494, 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 35 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, [all …]
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/Linux-v6.6/sound/pci/au88x0/ |
D | au8830.h | 18 #define NR_ADB 0x20 19 #define NR_SRC 0x10 20 #define NR_A3D 0x10 21 #define NR_MIXIN 0x20 22 #define NR_MIXOUT 0x10 23 #define NR_WT 0x40 26 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */ 27 #define POS_MASK 0x00000fff 28 #define POS_SHIFT 0x0 29 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ [all …]
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/Linux-v6.6/arch/x86/platform/ce4100/ |
D | falconfalls.dts | 16 #size-cells = <0>; 18 cpu@0 { 21 reg = <0>; 26 soc@0 { 36 reg = <0xfec00000 0x1000>; 41 reg = <0xfed00000 0x200>; 46 reg = <0xfee00000 0x1000>; 54 bus-range = <0 0>; 55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000 56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000 [all …]
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/Linux-v6.6/Documentation/devicetree/bindings/powerpc/fsl/ |
D | interlaken-lac.txt | 31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor" 32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the 45 IP Block Revision Register (IPBRR0) at offset 0x0BF8. 51 0x02000100 T4240 78 reg = <0x229000 0x1000>; 84 reg = <0x228000 0x1000>; 136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version 161 #address-cells = <0x1>; 162 #size-cells = <0x1>; 164 ranges = <0x0 0xf 0xf4400000 0x20000>; [all …]
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/Linux-v6.6/drivers/net/wireless/ath/ath10k/ |
D | coredump.c | 18 {0x800, 0x810}, 19 {0x820, 0x82C}, 20 {0x830, 0x8F4}, 21 {0x90C, 0x91C}, 22 {0xA14, 0xA18}, 23 {0xA84, 0xA94}, 24 {0xAA8, 0xAD4}, 25 {0xADC, 0xB40}, 26 {0x1000, 0x10A4}, 27 {0x10BC, 0x111C}, [all …]
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/Linux-v6.6/arch/arm/boot/dts/arm/ |
D | vexpress-v2m.dtsi | 27 ranges = <0x40000000 0x40000000 0x10000000>, 28 <0x10000000 0x10000000 0x00020000>; 31 interrupt-map-mask = <0 63>; 32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, [all …]
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/Linux-v6.6/drivers/net/ethernet/wangxun/libwx/ |
D | wx_type.h | 12 #define WX_NCSI_SUP 0x8000 13 #define WX_NCSI_MASK 0x8000 14 #define WX_WOL_SUP 0x4000 15 #define WX_WOL_MASK 0x4000 18 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF 19 #define WX_PCI_LINK_STATUS 0xB2 23 #define WX_MIS_PWR 0x10000 24 #define WX_MIS_RST 0x1000C 26 #define WX_MIS_RST_SW_RST BIT(0) 27 #define WX_MIS_ST 0x10028 [all …]
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/Linux-v6.6/drivers/net/ethernet/marvell/octeontx2/af/ |
D | rvu_reg.h | 12 #define RVU_AF_MSIXTR_BASE (0x10) 13 #define RVU_AF_ECO (0x20) 14 #define RVU_AF_BLK_RST (0x30) 15 #define RVU_AF_PF_BAR4_ADDR (0x40) 16 #define RVU_AF_RAS (0x100) 17 #define RVU_AF_RAS_W1S (0x108) 18 #define RVU_AF_RAS_ENA_W1S (0x110) 19 #define RVU_AF_RAS_ENA_W1C (0x118) 20 #define RVU_AF_GEN_INT (0x120) 21 #define RVU_AF_GEN_INT_W1S (0x128) [all …]
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/Linux-v6.6/drivers/clk/qcom/ |
D | gcc-sdx65.c | 36 .offset = 0x0, 39 .enable_reg = 0x6d000, 40 .enable_mask = BIT(0), 53 { 0x1, 2 }, 58 .offset = 0x0, 73 { P_BI_TCXO, 0 }, 91 { P_BI_TCXO, 0 }, 105 { P_BI_TCXO, 0 }, 119 { P_PCIE_PIPE_CLK, 0 }, 129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, [all …]
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/Linux-v6.6/arch/arm64/boot/dts/qcom/ |
D | qcs404.dtsi | 24 #clock-cells = <0>; 30 #clock-cells = <0>; 37 #size-cells = <0>; 42 reg = <0x100>; 56 reg = <0x101>; 70 reg = <0x102>; 84 reg = <0x103>; 104 CPU_SLEEP_0: cpu-sleep-0 { 107 arm,psci-suspend-param = <0x40000003>; 161 reg = <0 0x80000000 0 0>; [all …]
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