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/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-pcs-ufs-v5.h11 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
12 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
13 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
14 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
15 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
16 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
17 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
18 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
19 #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
20 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
[all …]
Dphy-qcom-qmp-pcs-ufs-v4.h10 #define QPHY_V4_PCS_UFS_PHY_START 0x000
11 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V4_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
16 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
/Linux-v6.1/Documentation/RCU/
Dlockdep-splat.rst30 rcu_scheduler_active = 1, debug_locks = 0
32 #0: (&shost->scan_mutex){+.+.}, at: [<ffffffff8145efca>]
33 scsi_scan_host_selected+0x5a/0x150
35 elevator_exit+0x22/0x60
37 cfq_exit_queue+0x43/0x190
40 Pid: 1552, comm: scsi_scan_6 Not tainted 3.0.0-rc5 #17
42 [<ffffffff810abb9b>] lockdep_rcu_dereference+0xbb/0xc0
43 [<ffffffff812b6139>] __cfq_exit_single_io_context+0xe9/0x120
44 [<ffffffff812b626c>] cfq_exit_queue+0x7c/0x190
45 [<ffffffff812a5046>] elevator_exit+0x36/0x60
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-ahb.txt9 Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
10 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should
11 be be <0x6000c000 0x150>.
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/Linux-v6.1/include/dt-bindings/clock/
Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8mp-tqma8mpql-mba8mpxl.dts24 io-channels = <&adc 0>, <&adc 1>;
42 pinctrl-0 = <&pinctrl_backlight>;
43 pwms = <&pwm2 0 5000000 0>;
44 brightness-levels = <0 4 8 16 32 64 128 255>;
54 pinctrl-0 = <&pinctrl_gpiobutton>;
73 pinctrl-0 = <&pinctrl_gpioled>;
75 led-0 {
78 function-enumerator = <0>;
104 pinctrl-0 = <&pinctrl_lvdsdisplay>;
114 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
[all …]
Dimx8mm-verdin.dtsi22 brightness-levels = <0 45 63 88 119 158 203 255>;
27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
37 #clock-cells = <0>;
44 pinctrl-0 = <&pinctrl_gpio_keys>;
100 pinctrl-0 = <&pinctrl_reg_eth>;
114 pinctrl-0 = <&pinctrl_reg_usb1_en>;
126 pinctrl-0 = <&pinctrl_reg_usb2_en>;
139 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
203 #size-cells = <0>;
[all …]
/Linux-v6.1/drivers/tty/serial/8250/
D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/Linux-v6.1/Documentation/fault-injection/
Dnvme-fault-injection.rst33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
/Linux-v6.1/drivers/clk/renesas/
Dr8a774a1-cpg-mssr.c78 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
99 DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074),
100 DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078),
101 DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268),
102 DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c),
103 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074),
104 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078),
105 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
106 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
115 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
Dr8a774b1-cpg-mssr.c96 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
97 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
98 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
99 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
100 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
101 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
102 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
103 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
112 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
113 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
Dr8a774e1-cpg-mssr.c78 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
99 DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074),
100 DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078),
101 DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268),
102 DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c),
103 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074),
104 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
105 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
106 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
116 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
Dr8a7796-cpg-mssr.c83 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
105 DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074),
106 DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078),
107 DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268),
108 DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c),
109 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074),
110 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
111 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
112 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
122 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
Dr8a77965-cpg-mssr.c100 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),
101 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),
102 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),
103 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),
104 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),
105 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
106 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
107 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
117 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
118 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
Dr8a7792-cpg-mssr.c80 DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
121 DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
167 * 0 0 0 15 x200/3 x208/2 x106
168 * 0 0 1 15 x200/3 x208/2 x88
169 * 0 1 0 20 x150/3 x156/2 x80
170 * 0 1 1 20 x150/3 x156/2 x66
171 * 1 0 0 26 / 2 x230/3 x240/2 x122
172 * 1 0 1 26 / 2 x230/3 x240/2 x102
173 * 1 1 0 30 / 2 x200/3 x208/2 x106
/Linux-v6.1/arch/arm/mach-davinci/
Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/Linux-v6.1/arch/mips/include/asm/
Dhpet.h9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
/Linux-v6.1/drivers/media/rc/keymaps/
Drc-x96max.c13 { 0x140, KEY_POWER },
22 { 0x118, KEY_VOLUMEUP },
23 { 0x110, KEY_VOLUMEDOWN },
25 { 0x143, KEY_MUTE }, // config
27 { 0x100, KEY_EPG }, // mouse
28 { 0x119, KEY_BACK },
30 { 0x116, KEY_UP },
31 { 0x151, KEY_LEFT },
32 { 0x150, KEY_RIGHT },
33 { 0x11a, KEY_DOWN },
[all …]
/Linux-v6.1/drivers/devfreq/event/
Dexynos-nocp.h13 NOCP_ID_REVISION_ID = 0x04,
14 NOCP_MAIN_CTL = 0x08,
15 NOCP_CFG_CTL = 0x0C,
17 NOCP_STAT_PERIOD = 0x24,
18 NOCP_STAT_GO = 0x28,
19 NOCP_STAT_ALARM_MIN = 0x2C,
20 NOCP_STAT_ALARM_MAX = 0x30,
21 NOCP_STAT_ALARM_STATUS = 0x34,
22 NOCP_STAT_ALARM_CLR = 0x38,
24 NOCP_COUNTERS_0_SRC = 0x138,
[all …]
/Linux-v6.1/drivers/media/platform/mediatek/jpeg/
Dmtk_jpeg_enc_hw.h15 #define JPEG_ENC_INT_STATUS_DONE BIT(0)
16 #define JPEG_ENC_INT_STATUS_MASK_ALLIRQ 0x13
18 #define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
20 #define JPEG_ENC_CTRL_YUV_FORMAT_MASK 0x18
24 #define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
25 #define JPEG_ENC_RESET_BIT BIT(0)
27 #define JPEG_ENC_YUV_FORMAT_YUYV 0
32 #define JPEG_ENC_QUALITY_Q60 0x0
33 #define JPEG_ENC_QUALITY_Q80 0x1
34 #define JPEG_ENC_QUALITY_Q90 0x2
[all …]
/Linux-v6.1/drivers/scsi/
Dfdomain_isa.c10 static int io[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
11 module_param_hw_array(io, int, ioport, NULL, 0);
12 MODULE_PARM_DESC(io, "base I/O address of controller (0x140, 0x150, 0x160, 0x170)");
14 static int irq[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
15 module_param_hw_array(irq, int, irq, NULL, 0);
16 MODULE_PARM_DESC(irq, "IRQ of controller (0=auto [default])");
18 static int scsi_id[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
19 module_param_hw_array(scsi_id, int, other, NULL, 0);
23 0xc8000,
24 0xca000,
[all …]

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