Home
last modified time | relevance | path

Searched +full:0 +full:x11e20000 (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-mt8192.yaml148 reg = <0x10005000 0x1000>,
149 <0x11c20000 0x1000>,
150 <0x11d10000 0x1000>,
151 <0x11d30000 0x1000>,
152 <0x11d40000 0x1000>,
153 <0x11e20000 0x1000>,
154 <0x11e70000 0x1000>,
155 <0x11ea0000 0x1000>,
156 <0x11f20000 0x1000>,
157 <0x11f30000 0x1000>,
[all …]
Dmediatek,mt6779-pinctrl.yaml77 '-[0-9]*$':
120 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
121 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
122 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
125 enum: [0, 1, 2, 3]
131 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
132 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
133 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
136 enum: [0, 1, 2, 3]
157 reg = <0 0x10005000 0 0x1000>,
[all …]
Dmediatek,mt8188-pinctrl.yaml182 reg = <0x10005000 0x1000>,
183 <0x11c00000 0x1000>,
184 <0x11e10000 0x1000>,
185 <0x11e20000 0x1000>,
186 <0x11ea0000 0x1000>,
187 <0x1000b000 0x1000>;
193 gpio-ranges = <&pio 0 0 176>;
195 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
Dpinctrl-mt8195.yaml241 reg = <0x10005000 0x1000>,
242 <0x11d10000 0x1000>,
243 <0x11d30000 0x1000>,
244 <0x11d40000 0x1000>,
245 <0x11e20000 0x1000>,
246 <0x11eb0000 0x1000>,
247 <0x11f40000 0x1000>,
248 <0x1000b000 0x1000>;
254 gpio-ranges = <&pio 0 0 144>;
256 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
Dmediatek,mt7986-pinctrl.yaml86 "watchdog" "watchdog" 0
304 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
307 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
308 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
309 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
312 enum: [0, 1, 2, 3]
316 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
319 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
320 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
321 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
[all …]
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
Dmt7986a.dtsi17 clk40m: oscillator@0 {
20 #clock-cells = <0>;
26 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x0>;
39 reg = <0x1>;
47 reg = <0x2>;
55 reg = <0x3>;
71 reg = <0 0x43000000 0 0x30000>;
77 reg = <0 0x4fc00000 0 0x00100000>;
[all …]
Dmt8192.dtsi34 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x000>;
64 reg = <0x100>;
75 reg = <0x200>;
86 reg = <0x300>;
97 reg = <0x400>;
108 reg = <0x500>;
[all …]
Dmt8195.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0x000>;
37 performance-domains = <&performance 0>;
48 reg = <0x100>;
50 performance-domains = <&performance 0>;
61 reg = <0x200>;
63 performance-domains = <&performance 0>;
74 reg = <0x300>;
76 performance-domains = <&performance 0>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dexynos3250.dtsi51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0>;
111 xusbxti: clock-0 {
113 clock-frequency = <0>;
114 #clock-cells = <0>;
120 clock-frequency = <0>;
121 #clock-cells = <0>;
127 clock-frequency = <0>;
128 #clock-cells = <0>;
[all …]
Dexynos4.dtsi68 reg = <0x03810000 0x0C>;
79 reg = <0x03830000 0x100>;
88 samsung,idma-addr = <0x03000000>;
95 reg = <0x10000000 0x100>;
100 reg = <0x10500000 0x2000>;
105 reg = <0x12570000 0x14>;
116 reg = <0x10023C40 0x20>;
117 #power-domain-cells = <0>;
123 reg = <0x10023C60 0x20>;
124 #power-domain-cells = <0>;
[all …]
/Linux-v6.1/drivers/pinctrl/mediatek/
Dpinctrl-mt7986.c11 #define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
17 _x_bits, 32, 0)
23 * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
24 * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
76 PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
80 PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
84 PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
88 PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
92 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
93 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
[all …]
Dpinctrl-mt6779.c13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
21 32, 0)
28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
[all …]
Dpinctrl-mt8195.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000,
14 * iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000,
15 * iocfg[6]:0x11f40000.
21 32, 0)
28 PIN_FIELD(0, 144, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 144, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 144, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 144, 0x100, 0x10, 0, 1),
44 PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1),
45 PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1),
[all …]
Dpinctrl-mt8192.c13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000,
14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000,
15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000,
16 * iocfg_tl:0x11F30000
22 32, 0)
29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
[all …]
Dpinctrl-mt8188.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11c00000, iocfg[2]:0x11e10000,
14 * iocfg[3]:0x11e20000, iocfg[4]:0x11ea0000
20 32, 0)
27 PIN_FIELD(0, 177, 0x0300, 0x10, 0, 4),
31 PIN_FIELD(0, 177, 0x0000, 0x10, 0, 1),
35 PIN_FIELD(0, 177, 0x0200, 0x10, 0, 1),
39 PIN_FIELD(0, 177, 0x0100, 0x10, 0, 1),
43 PIN_FIELD_BASE(0, 0, 1, 0x0170, 0x10, 8, 1),
44 PIN_FIELD_BASE(1, 1, 1, 0x0170, 0x10, 9, 1),
45 PIN_FIELD_BASE(2, 2, 1, 0x0170, 0x10, 10, 1),
[all …]