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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Drenesas,rzg2l-cpg.yaml59 const: 0
82 reg = <0x11010000 0x10000>;
86 #power-domain-cells = <0>;
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dmicrochip,sparx5-switch.yaml34 pattern: "^switch@[0-9a-f]+$"
83 const: 0
86 "^port@[0-9a-f]+$":
111 minimum: 0
142 reg = <0 0x401000>,
143 <0x10004000 0x7fc000>,
144 <0x11010000 0xaf0000>;
148 resets = <&reset 0>;
152 #size-cells = <0>;
154 port0: port@0 {
[all …]
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt6797.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x000>;
38 reg = <0x001>;
45 reg = <0x002>;
52 reg = <0x003>;
59 reg = <0x100>;
66 reg = <0x101>;
73 reg = <0x102>;
80 reg = <0x103>;
[all …]
Dmt8186.dtsi23 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x000>;
78 reg = <0x100>;
90 reg = <0x200>;
102 reg = <0x300>;
114 reg = <0x400>;
126 reg = <0x500>;
138 reg = <0x600>;
150 reg = <0x700>;
[all …]
Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]
Dmt8192.dtsi34 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x000>;
64 reg = <0x100>;
75 reg = <0x200>;
86 reg = <0x300>;
97 reg = <0x400>;
108 reg = <0x500>;
[all …]
Dmt8183.dtsi293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
346 reg = <0x001>;
362 reg = <0x002>;
378 reg = <0x003>;
394 reg = <0x100>;
410 reg = <0x101>;
426 reg = <0x102>;
442 reg = <0x103>;
[all …]
Dmt8195.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0x000>;
37 performance-domains = <&performance 0>;
48 reg = <0x100>;
50 performance-domains = <&performance 0>;
61 reg = <0x200>;
63 performance-domains = <&performance 0>;
74 reg = <0x300>;
76 performance-domains = <&performance 0>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/microchip/
Dsparx5.dtsi28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0 0x0>;
49 reg = <0x0 0x1>;
79 #clock-cells = <0>;
87 reg = <0x6 0x1110000c 0x24>;
92 #clock-cells = <0>;
98 #clock-cells = <0>;
114 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
115 <0x6 0x00340000 0xc0000>, /* GICR */
[all …]
/Linux-v6.1/arch/arm64/boot/dts/renesas/
Dr9a07g043.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/Linux-v6.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Drk322x.dtsi26 #size-cells = <0>;
31 reg = <0xf00>;
43 reg = <0xf01>;
53 reg = <0xf02>;
63 reg = <0xf03>;
71 cpu0_opp_table: opp-table-0 {
127 #clock-cells = <0>;
137 reg = <0x100b0000 0x4000>;
144 pinctrl-0 = <&i2s1_bus>;
150 reg = <0x100c0000 0x4000>;
[all …]