Searched +full:0 +full:x11010000 (Results 1 – 11 of 11) sorted by relevance
| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | renesas,rzg2l-cpg.yaml | 54 const: 0
77 reg = <0x11010000 0x10000>;
81 #power-domain-cells = <0>;
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| /Linux-v5.15/Documentation/devicetree/bindings/net/ |
| D | microchip,sparx5-switch.yaml | 34 pattern: "^switch@[0-9a-f]+$"
76 "^port@[0-9a-f]+$":
83 const: 0
123 minimum: 0
156 reg = <0 0x401000>,
157 <0x10004000 0x7fc000>,
158 <0x11010000 0xaf0000>;
162 resets = <&reset 0>;
166 #size-cells = <0>;
168 port0: port@0 {
[all …]
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| /Linux-v5.15/arch/arm64/boot/dts/renesas/ |
| D | r9a07g044.dtsi | 19 #clock-cells = <0>;
20 clock-frequency = <0>;
26 #clock-cells = <0>;
28 clock-frequency = <0>;
38 #size-cells = <0>;
51 cpu0: cpu@0 {
53 reg = <0>;
61 reg = <0x100>;
67 L3_CA55: cache-controller-0 {
70 cache-size = <0x40000>;
[all …]
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| /Linux-v5.15/arch/arm64/boot/dts/mediatek/ |
| D | mt6797.dtsi | 25 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x000>;
38 reg = <0x001>;
45 reg = <0x002>;
52 reg = <0x003>;
59 reg = <0x100>;
66 reg = <0x101>;
73 reg = <0x102>;
80 reg = <0x103>;
[all …]
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| D | mt8192.dtsi | 20 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x000>;
50 reg = <0x100>;
61 reg = <0x200>;
72 reg = <0x300>;
83 reg = <0x400>;
94 reg = <0x500>;
[all …]
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| D | mt2712e.dtsi | 66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
154 #clock-cells = <0>;
[all …]
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| D | mt8173.dtsi | 136 #size-cells = <0>;
158 cpu0: cpu@0 {
161 reg = <0x000>;
176 reg = <0x001>;
191 reg = <0x100>;
206 reg = <0x101>;
221 CPU_SLEEP_0: cpu-sleep-0 {
227 arm,psci-suspend-param = <0x0010000>;
249 cpu_suspend = <0x84000001>;
250 cpu_off = <0x84000002>;
[all …]
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| D | mt8183.dtsi | 47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x000>;
95 reg = <0x001>;
106 reg = <0x002>;
117 reg = <0x003>;
128 reg = <0x100>;
139 reg = <0x101>;
150 reg = <0x102>;
161 reg = <0x103>;
[all …]
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| /Linux-v5.15/arch/arm64/boot/dts/microchip/ |
| D | sparx5.dtsi | 28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0 0x0>;
49 reg = <0x0 0x1>;
79 #clock-cells = <0>;
87 reg = <0x6 0x1110000c 0x24>;
92 #clock-cells = <0>;
98 #clock-cells = <0>;
114 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
115 <0x6 0x00340000 0xc0000>, /* GICR */
[all …]
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| /Linux-v5.15/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_main.c | 54 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
55 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
56 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
57 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
58 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
59 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
60 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
61 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
62 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
63 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | rk322x.dtsi | 26 #size-cells = <0>;
31 reg = <0xf00>;
43 reg = <0xf01>;
53 reg = <0xf02>;
63 reg = <0xf03>;
127 #clock-cells = <0>;
137 reg = <0x100b0000 0x4000>;
144 pinctrl-0 = <&i2s1_bus>;
150 reg = <0x100c0000 0x4000>;
161 reg = <0x100d0000 0x1000>;
[all …]
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