Searched +full:0 +full:x10500000 (Results 1 – 11 of 11) sorted by relevance
51 reg = <0x52800000 0x100000>;56 #size-cells = <0>;57 cros-ec@0 {59 reg = <0>;68 reg = <0x0 0x10500000 0x80000>;
114 reg = <0x10500000 0x80000>,115 <0x10700000 0x8000>,116 <0x10720000 0xe0000>;
20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */29 #define AR2315_MISC_IRQ_UART0 043 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */44 #define AR2315_SPI_READ_SIZE 0x0100000045 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */[all …]
35 #clock-cells = <0>;41 reg = <0x10090000 0x10000>;52 reg = <0x10104000 0x800>;64 reg = <0x10138000 0x1000>;71 reg = <0x1013c000 0x100>;76 reg = <0x1013c200 0x20>;90 reg = <0x1013c600 0x20>;99 reg = <0x1013d000 0x1000>,100 <0x1013c100 0x0100>;105 reg = <0x10124000 0x400>;[all …]
34 #size-cells = <0>;40 reg = <0xf00>;53 reg = <0xf01>;84 #clock-cells = <0>;89 reg = <0x10080000 0x2000>;92 ranges = <0 0x10080000 0x2000>;94 smp-sram@0 {96 reg = <0x00 0x10>;102 reg = <0x10090000 0x10000>;122 reg = <0x10108000 0x800>;[all …]
68 reg = <0x03810000 0x0C>;79 reg = <0x03830000 0x100>;88 samsung,idma-addr = <0x03000000>;95 reg = <0x10000000 0x100>;100 reg = <0x10500000 0x2000>;105 reg = <0x12570000 0x14>;116 reg = <0x10023C40 0x20>;117 #power-domain-cells = <0>;123 reg = <0x10023C60 0x20>;124 #power-domain-cells = <0>;[all …]
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */[all …]
23 #size-cells = <0>;63 cpu0: cpu@0 {66 reg = <0x000>;78 reg = <0x100>;90 reg = <0x200>;102 reg = <0x300>;114 reg = <0x400>;126 reg = <0x500>;138 reg = <0x600>;150 reg = <0x700>;[all …]
34 #clock-cells = <0>;41 #clock-cells = <0>;48 #size-cells = <0>;50 cpu0: cpu@0 {53 reg = <0x000>;64 reg = <0x100>;75 reg = <0x200>;86 reg = <0x300>;97 reg = <0x400>;108 reg = <0x500>;[all …]
293 #size-cells = <0>;327 cpu0: cpu@0 {330 reg = <0x000>;346 reg = <0x001>;362 reg = <0x002>;378 reg = <0x003>;394 reg = <0x100>;410 reg = <0x101>;426 reg = <0x102>;442 reg = <0x103>;[all …]
30 #size-cells = <0>;32 cpu0: cpu@0 {35 reg = <0x000>;37 performance-domains = <&performance 0>;48 reg = <0x100>;50 performance-domains = <&performance 0>;61 reg = <0x200>;63 performance-domains = <&performance 0>;74 reg = <0x300>;76 performance-domains = <&performance 0>;[all …]
