Searched +full:0 +full:x10500000 (Results 1 – 6 of 6) sorted by relevance
31 reg = <0 0x10500000 0 0x80000>,32 <0 0x105c0000 0 0x5000>;
50 reg = <0x52800000 0x100000>;55 #size-cells = <0>;56 cros-ec@0 {58 reg = <0>;67 reg = <0x0 0x10500000 0x80000>;
20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */29 #define AR2315_MISC_IRQ_UART0 043 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */44 #define AR2315_SPI_READ_SIZE 0x0100000045 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */[all …]
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */[all …]
38 #size-cells = <0>;72 cpu0: cpu@0 {75 reg = <0x000>;86 reg = <0x001>;97 reg = <0x002>;108 reg = <0x003>;119 reg = <0x100>;130 reg = <0x101>;141 reg = <0x102>;152 reg = <0x103>;[all …]
68 reg = <0x03810000 0x0C>;79 reg = <0x03830000 0x100>;88 samsung,idma-addr = <0x03000000>;95 reg = <0x10000000 0x100>;100 reg = <0x10500000 0x2000>;105 reg = <0x12570000 0x14>;116 reg = <0x10023C40 0x20>;117 #power-domain-cells = <0>;123 reg = <0x10023C60 0x20>;124 #power-domain-cells = <0>;[all …]
