Searched +full:0 +full:x10300000 (Results 1 – 8 of 8) sorted by relevance
79 "^r[0-9]+":100 "^b[0-9]+$":170 wifi@0,0 {172 reg = <0x0000 0 0 0 0>;174 mediatek,mtd-eeprom = <&factory 0x8000>;209 reg = <0x10300000 0x100000>;214 mediatek,mtd-eeprom = <&factory 0x0>;222 reg = <0x10300000 0x100000>;
17 #define RTL8712_IOBASE_TXPKT 0x10200000 /*IOBASE_TXPKT*/18 #define RTL8712_IOBASE_RXPKT 0x10210000 /*IOBASE_RXPKT*/19 #define RTL8712_IOBASE_RXCMD 0x10220000 /*IOBASE_RXCMD*/20 #define RTL8712_IOBASE_TXSTATUS 0x10230000 /*IOBASE_TXSTATUS*/21 #define RTL8712_IOBASE_RXSTATUS 0x10240000 /*IOBASE_RXSTATUS*/22 #define RTL8712_IOBASE_IOREG 0x10250000 /*IOBASE_IOREG ADDR*/23 #define RTL8712_IOBASE_SCHEDULER 0x10260000 /*IOBASE_SCHEDULE*/25 #define RTL8712_IOBASE_TRXDMA 0x10270000 /*IOBASE_TRXDMA*/26 #define RTL8712_IOBASE_TXLLT 0x10280000 /*IOBASE_TXLLT*/27 #define RTL8712_IOBASE_WMAC 0x10290000 /*IOBASE_WMAC*/[all …]
10 #size-cells = <0>;12 cpu@0 {15 reg = <0>;25 #address-cells = <0>;33 reg = <0x10000000 0x200000>;34 ranges = <0x0 0x10000000 0x1FFFFF>;39 sysc: system-controller@0 {41 reg = <0x0 0x60>;46 reg = <0x60 0x8>;48 #size-cells = <0>;[all …]
17 #clock-cells = <0>;23 #clock-cells = <0>;28 #address-cells = <0x1>;29 #size-cells = <0x0>;31 CPU0: cpu@0 {34 reg = <0x0>;43 reg = <0x1>;51 reg = <0x2>;59 reg = <0x3>;65 cache-level = <0x2>;[all …]
20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */29 #define AR2315_MISC_IRQ_UART0 043 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */44 #define AR2315_SPI_READ_SIZE 0x0100000045 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */[all …]
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */[all …]
29 #size-cells = <0>;34 reg = <0xf00>;85 #clock-cells = <0>;96 reg = <0x102a0000 0x4000>;97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;108 reg = <0x10080000 0x2000>;111 ranges = <0 0x10080000 0x2000>;116 reg = <0x10210000 0x100>;125 pinctrl-0 = <&uart2m0_xfer>;131 reg = <0x10220000 0x100>;[all …]
131 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3132 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0133 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */163 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3164 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0165 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3167 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF286 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1287 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0288 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1[all …]
