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/Linux-v6.1/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc512x_lpbfifo.txt16 reg = <0x10100 0x50>;
17 interrupts = <7 0x8>;
/Linux-v6.1/Documentation/devicetree/bindings/mips/cavium/
Dciu3.txt24 #address-cells = <0>;
26 reg = <0x10100 0x00000000 0x0 0xb0000000>;
/Linux-v6.1/arch/m68k/include/asm/
Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/arm/
Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
Didle-states.yaml102 between 0 and infinite time, until a wake-up event occurs.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
167 0| 1 time(ms)
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
380 #size-cells = <0>;
383 cpu@0 {
386 reg = <0x0 0x0>;
395 reg = <0x0 0x1>;
404 reg = <0x0 0x100>;
413 reg = <0x0 0x101>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dorion5x.dtsi24 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
25 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
28 clocks = <&core_clk 0>;
34 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
35 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
38 clocks = <&core_clk 0>;
44 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
45 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
48 clocks = <&core_clk 0>;
54 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
[all …]
Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/arm/
Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x000>;
54 reg = <0x0 0x100>;
60 reg = <0x0 0x200>;
66 reg = <0x0 0x300>;
72 reg = <0x0 0x10000>;
78 reg = <0x0 0x10100>;
84 reg = <0x0 0x10200>;
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/
Dmpc5125twr.dts30 #size-cells = <0>;
32 PowerPC,5125@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
36 i-cache-line-size = <0x20>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x00000000 0x10000000>; // 256MB at 0
52 reg = <0x30000000 0x08000>; // 32K at 0x30000000
57 #size-cells = <0>;
[all …]
Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
[all …]
/Linux-v6.1/drivers/rapidio/switches/
Didt_gen3.c18 #define RIO_EM_PW_STAT 0x40020
19 #define RIO_PW_CTL 0x40204
20 #define RIO_PW_CTL_PW_TMR 0xffffff00
21 #define RIO_PW_ROUTE 0x40208
23 #define RIO_EM_DEV_INT_EN 0x40030
25 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
26 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
28 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
29 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
30 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/octeon_ep/
Doctep_regs_cn9k_pf.h12 #define CN93_RST_BOOT 0x000087E006001600ULL
13 #define CN93_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL
14 #define CN93_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL
16 #define CN93_CONFIG_XPANSION_BAR 0x38
17 #define CN93_CONFIG_PCIE_CAP 0x70
18 #define CN93_CONFIG_PCIE_DEVCAP 0x74
19 #define CN93_CONFIG_PCIE_DEVCTL 0x78
20 #define CN93_CONFIG_PCIE_LINKCAP 0x7C
21 #define CN93_CONFIG_PCIE_LINKCTL 0x80
22 #define CN93_CONFIG_PCIE_SLOTCAP 0x84
[all …]
/Linux-v6.1/drivers/crypto/marvell/octeontx2/
Dotx2_cpt_hw_types.h11 #define OTX2_CPT_PCI_PF_DEVICE_ID 0xA0FD
12 #define OTX2_CPT_PCI_VF_DEVICE_ID 0xA0FE
13 #define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2
14 #define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3
29 #define OTX2_CPT_VF_INTR_MBOX_MASK BIT(0)
30 #define CN10K_CPT_VF_MBOX_REGION (0xC0000)
36 #define OTX2_CPT_PF_CONSTANTS (0x0)
37 #define OTX2_CPT_PF_RESET (0x100)
38 #define OTX2_CPT_PF_DIAG (0x120)
39 #define OTX2_CPT_PF_BIST_STATUS (0x160)
[all …]
/Linux-v6.1/arch/arm64/boot/dts/apple/
Dt8103.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0 0x0>;
30 cpu-release-addr = <0 0>; /* To be filled by loader */
36 reg = <0x0 0x1>;
38 cpu-release-addr = <0 0>; /* To be filled by loader */
44 reg = <0x0 0x2>;
46 cpu-release-addr = <0 0>; /* To be filled by loader */
52 reg = <0x0 0x3>;
54 cpu-release-addr = <0 0>; /* To be filled by loader */
[all …]
/Linux-v6.1/drivers/scsi/qla4xxx/
Dql4_nx.h13 #define PHAN_INITIALIZE_FAILED 0xffff
14 #define PHAN_INITIALIZE_COMPLETE 0xff01
17 #define PHAN_INITIALIZE_ACK 0xf00f
18 #define PHAN_PEG_RCV_INITIALIZED 0xff01
21 #define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))
23 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
24 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
25 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
26 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
31 #define qla82xx_get_temp_state(x) ((x) & 0xffff)
[all …]
/Linux-v6.1/drivers/dma/
Dapple-admac.c24 #define RING_WRITE_SLOT GENMASK(1, 0)
30 #define STATUS_DESC_DONE BIT(0)
35 #define REG_TX_START 0x0000
36 #define REG_TX_STOP 0x0004
37 #define REG_RX_START 0x0008
38 #define REG_RX_STOP 0x000c
40 #define REG_CHAN_CTL(ch) (0x8000 + (ch) * 0x200)
41 #define REG_CHAN_CTL_RST_RINGS BIT(0)
43 #define REG_DESC_RING(ch) (0x8070 + (ch) * 0x200)
44 #define REG_REPORT_RING(ch) (0x8074 + (ch) * 0x200)
[all …]
/Linux-v6.1/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hdr.h20 QLCNIC_HW_H0_CH_HUB_ADR = 0x05,
21 QLCNIC_HW_H1_CH_HUB_ADR = 0x0E,
22 QLCNIC_HW_H2_CH_HUB_ADR = 0x03,
23 QLCNIC_HW_H3_CH_HUB_ADR = 0x01,
24 QLCNIC_HW_H4_CH_HUB_ADR = 0x06,
25 QLCNIC_HW_H5_CH_HUB_ADR = 0x07,
26 QLCNIC_HW_H6_CH_HUB_ADR = 0x08
29 /* Hub 0 */
31 QLCNIC_HW_MN_CRB_AGT_ADR = 0x15,
32 QLCNIC_HW_MS_CRB_AGT_ADR = 0x25
[all …]
/Linux-v6.1/drivers/scsi/qla2xxx/
Dqla_nx.h15 #define PHAN_INITIALIZE_FAILED 0xffff
16 #define PHAN_INITIALIZE_COMPLETE 0xff01
19 #define PHAN_INITIALIZE_ACK 0xf00f
20 #define PHAN_PEG_RCV_INITIALIZED 0xff01
23 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
26 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
27 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
28 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
29 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
30 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
[all …]
/Linux-v6.1/drivers/net/ethernet/qlogic/netxen/
Dnetxen_nic_hdr.h21 NETXEN_HW_H0_CH_HUB_ADR = 0x05,
22 NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
23 NETXEN_HW_H2_CH_HUB_ADR = 0x03,
24 NETXEN_HW_H3_CH_HUB_ADR = 0x01,
25 NETXEN_HW_H4_CH_HUB_ADR = 0x06,
26 NETXEN_HW_H5_CH_HUB_ADR = 0x07,
27 NETXEN_HW_H6_CH_HUB_ADR = 0x08
30 /* Hub 0 */
32 NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
33 NETXEN_HW_MS_CRB_AGT_ADR = 0x25
[all …]
/Linux-v6.1/arch/arm64/boot/dts/renesas/
Dr8a779f0.dtsi19 #size-cells = <0>;
59 a55_0: cpu@0 {
61 reg = <0>;
72 reg = <0x100>;
83 reg = <0x10000>;
94 reg = <0x10100>;
105 reg = <0x20000>;
116 reg = <0x20100>;
127 reg = <0x30000>;
138 reg = <0x30100>;
[all …]
/Linux-v6.1/drivers/gpu/drm/ast/
Dast_post.c44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); in ast_enable_vga()
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); in ast_enable_vga()
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_enable_mmio()
63 return !!(ch & 0x01); in ast_is_vga_enabled()
66 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
67 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
68 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
79 for (i = 0x81; i <= 0x9f; i++) in ast_set_def_ext_reg()
80 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
84 if (pdev->revision >= 0x20) in ast_set_def_ext_reg()
[all …]
/Linux-v6.1/arch/arm64/boot/dts/hisilicon/
Dhip06.dtsi23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
[all …]
/Linux-v6.1/drivers/net/ethernet/mediatek/
Dmtk_eth_soc.h28 #define MTK_TX_DMA_BUF_LEN 0x3fff
29 #define MTK_TX_DMA_BUF_LEN_V2 0xffff
34 #define MTK_DMA_DUMMY_DESC 0xffffffff
59 #define MTK_QRX_OFFSET 0x10
76 #define MTK_RST_GL 0x04
77 #define RST_GL_PSE BIT(0)
80 #define MTK_INT_STATUS2 0x08
85 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
88 #define MTK_FE_INT_GRP 0x20
91 #define MTK_CDMQ_IG_CTRL 0x1400
[all …]
/Linux-v6.1/arch/arm64/boot/dts/exynos/
Dexynosautov9.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0>;
91 reg = <0x100>;
98 reg = <0x200>;
105 reg = <0x300>;
112 reg = <0x10000>;
119 reg = <0x10100>;
126 reg = <0x10200>;
133 reg = <0x10300>;
[all …]

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