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/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dspi-sifive.yaml62 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
77 reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
82 #size-cells = <0>;
/Linux-v5.15/Documentation/devicetree/bindings/arm/samsung/
Dpmu.yaml62 pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$'
121 reg = <0x10040000 0x5000>;
/Linux-v5.15/arch/arm/boot/dts/
Dstm32mp157a-microgea-stm32mp1.dtsi13 reg = <0xc0000000 0x10000000>;
23 reg = <0x10000000 0x40000>;
29 reg = <0x10040000 0x1000>;
35 reg = <0x10041000 0x1000>;
41 reg = <0x10042000 0x4000>;
47 reg = <0x30000000 0x40000>;
53 reg = <0x38000000 0x10000>;
100 pinctrl-0 = <&fmc_pins_a>;
104 nand-controller@4,0 {
107 nand@0 {
[all …]
Darm-realview-eb.dts31 arm,hbi = <0x140>;
56 reg = <0x10041000 0x1000>,
57 <0x10040000 0x100>;
69 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
74 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
79 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
84 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
85 <0 18 IRQ_TYPE_LEVEL_HIGH>;
90 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
95 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
[all …]
Dstm32mp157a-icore-stm32mp1.dtsi13 reg = <0xc0000000 0x20000000>;
23 reg = <0x10000000 0x40000>;
29 reg = <0x10040000 0x1000>;
35 reg = <0x10041000 0x1000>;
41 reg = <0x10042000 0x4000>;
47 reg = <0x30000000 0x40000>;
53 reg = <0x38000000 0x10000>;
159 pinctrl-0 = <&i2c2_pins_a>;
176 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
Dstm32mp15xx-osd32.dtsi19 reg = <0x10000000 0x40000>;
25 reg = <0x10040000 0x1000>;
31 reg = <0x10041000 0x1000>;
37 reg = <0x10042000 0x4000>;
43 reg = <0x30000000 0x40000>;
49 reg = <0x38000000 0x10000>;
63 pinctrl-0 = <&i2c4_pins_a>;
72 reg = <0x33>;
73 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
89 regulator-initial-mode = <0>;
[all …]
Darm-realview-eb-mp.dtsi46 reg = <0x1f001000 0x1000>,
47 <0x1f000100 0x100>;
56 reg = <0x10041000 0x1000>,
57 <0x10040000 0x100>;
59 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
64 reg = <0x1f002000 0x1000>;
66 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
67 <0 30 IRQ_TYPE_LEVEL_HIGH>,
68 <0 31 IRQ_TYPE_LEVEL_HIGH>;
88 reg = <0x1f000000 0x100>;
[all …]
Dstm32mp157c-odyssey-som.dtsi22 reg = <0xc0000000 0x20000000>;
32 reg = <0x10000000 0x40000>;
38 reg = <0x10040000 0x1000>;
44 reg = <0x10041000 0x1000>;
50 reg = <0x10042000 0x4000>;
56 reg = <0x30000000 0x40000>;
62 reg = <0x38000000 0x10000>;
67 reg = <0xd4000000 0x4000000>;
90 pinctrl-0 = <&i2c2_pins_a>;
100 reg = <0x33>;
[all …]
Dstm32mp157c-ed1.dts25 reg = <0xC0000000 0x40000000>;
35 reg = <0x10000000 0x40000>;
41 reg = <0x10040000 0x1000>;
47 reg = <0x10041000 0x1000>;
53 reg = <0x10042000 0x4000>;
59 reg = <0x30000000 0x40000>;
65 reg = <0x38000000 0x10000>;
70 reg = <0xe8000000 0x8000000>;
88 gpios-states = <0>;
89 states = <1800000 0x1>,
[all …]
Dexynos5410.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
43 reg = <0x1>;
50 reg = <0x2>;
57 reg = <0x3>;
70 reg = <0x10040000 0x5000>;
78 reg = <0x10010000 0x30000>;
84 reg = <0x03810000 0x0C>;
92 reg = <0x10060000 0x100>;
[all …]
Dstm32mp15xx-dhcom-som.dtsi21 reg = <0xC0000000 0x40000000>;
31 reg = <0x10000000 0x40000>;
37 reg = <0x10040000 0x1000>;
43 reg = <0x10041000 0x1000>;
49 reg = <0x10042000 0x4000>;
55 reg = <0x30000000 0x40000>;
61 reg = <0x38000000 0x10000>;
84 adc1: adc@0 {
86 st,adc-channels = <0>;
103 pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
[all …]
Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
81 #clock-cells = <0>;
89 #clock-cells = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
113 pclk: pclk@0 {
114 #clock-cells = <0>;
[all …]
Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]
Dstm32mp15xx-dkx.dtsi13 reg = <0xc0000000 0x20000000>;
23 reg = <0x10000000 0x40000>;
29 reg = <0x10040000 0x1000>;
35 reg = <0x10041000 0x1000>;
41 reg = <0x10042000 0x4000>;
47 reg = <0x30000000 0x40000>;
53 reg = <0x38000000 0x10000>;
58 reg = <0xd4000000 0x4000000>;
95 pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
100 adc1: adc@0 {
[all …]
Dexynos5250.dtsi51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0>;
180 reg = <0x02020000 0x30000>;
183 ranges = <0 0x02020000 0x30000>;
185 smp-sram@0 {
187 reg = <0x0 0x1000>;
192 reg = <0x2f000 0x1000>;
198 reg = <0x10044000 0x20>;
199 #power-domain-cells = <0>;
[all …]
Dexynos5420.dtsi162 reg = <0x10d20000 0x1000>;
163 ranges = <0x0 0x10d20000 0x6000>;
168 reg = <0x4000 0x1000>;
173 reg = <0x5000 0x1000>;
179 reg = <0x10010000 0x30000>;
185 reg = <0x03810000 0x0C>;
195 reg = <0x11000000 0x10000>;
208 #size-cells = <0>;
209 reg = <0x12200000 0x2000>;
212 fifo-depth = <0x40>;
[all …]
/Linux-v5.15/arch/arm/mach-imx/
Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/Linux-v5.15/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/Linux-v5.15/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
144 compatible = "sifive,plic-1.0.0";
145 reg = <0x0 0xc000000 0x0 0x4000000>;
149 &cpu0_intc 0xffffffff
150 &cpu1_intc 0xffffffff &cpu1_intc 9
151 &cpu2_intc 0xffffffff &cpu2_intc 9
152 &cpu3_intc 0xffffffff &cpu3_intc 9
153 &cpu4_intc 0xffffffff &cpu4_intc 9>;
[all …]
Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
56 reg = <0x1>;
80 reg = <0x2>;
104 reg = <0x3>;
128 reg = <0x4>;
145 #address-cells = <0>;
146 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
147 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt49 which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
196 #clock-cells = <0>;
203 reg = <0x10030000 0x0c04>;
218 reg = <0x10fc0000 0x0c04>;
227 reg = <0x105b0000 0x100c>;
238 reg = <0x14c80000 0x0b08>;
244 reg = <0x10040000 0x0b20>;
250 reg = <0x156e0000 0x0b04>;
277 reg = <0x12460000 0x0b08>;
291 reg = <0x13b90000 0x0c04>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi45 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu_atlas0: cpu@0 {
55 reg = <0x0>;
57 i-cache-size = <0xc000>;
60 d-cache-size = <0x8000>;
69 reg = <0x1>;
71 i-cache-size = <0xc000>;
74 d-cache-size = <0x8000>;
83 reg = <0x2>;
[all …]
/Linux-v5.15/drivers/net/wan/
Dwanxlfw.S2 .psize 0
14 0x000 - 0x050 TX#0 0x050 - 0x140 RX#0
15 0x140 - 0x190 TX#1 0x190 - 0x280 RX#1
16 0x280 - 0x2D0 TX#2 0x2D0 - 0x3C0 RX#2
17 0x3C0 - 0x410 TX#3 0x410 - 0x500 RX#3
43 PCI9060_VECTOR = 0x0000006C
44 CPM_IRQ_BASE = 0x40
46 SCC1_VECTOR = (CPM_IRQ_BASE + 0x1E) * 4
47 SCC2_VECTOR = (CPM_IRQ_BASE + 0x1D) * 4
48 SCC3_VECTOR = (CPM_IRQ_BASE + 0x1C) * 4
[all …]
/Linux-v5.15/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main.c54 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
55 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
56 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
57 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
58 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
59 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
60 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
61 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
62 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
63 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/Linux-v5.15/drivers/clk/samsung/
Dclk-exynos7.c13 /* Register Offset definitions for CMU_TOPC (0x10570000) */
14 #define CC_PLL_LOCK 0x0000
15 #define BUS0_PLL_LOCK 0x0004
16 #define BUS1_DPLL_LOCK 0x0008
17 #define MFC_PLL_LOCK 0x000C
18 #define AUD_PLL_LOCK 0x0010
19 #define CC_PLL_CON0 0x0100
20 #define BUS0_PLL_CON0 0x0110
21 #define BUS1_DPLL_CON0 0x0120
22 #define MFC_PLL_CON0 0x0130
[all …]

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