Searched +full:0 +full:x10011000 (Results 1 – 9 of 9) sorted by relevance
48 const: 0x104c51 const: 0xb00d88 reg = <0x00 0x02900000 0x00 0x1000>,89 <0x00 0x02907000 0x00 0x400>,90 <0x00 0x0d000000 0x00 0x00800000>,91 <0x00 0x10000000 0x00 0x00001000>;102 bus-range = <0x0 0xf>;103 vendor-id = <0x104c>;104 device-id = <0xb00d>;105 msi-map = <0x0 &gic_its 0x0 0x10000>;[all …]
12 reg = <0 0x10011000 0 0x1000>;
24 #size-cells = <0>;25 cpu0: cpu@0 {31 reg = <0>;144 compatible = "sifive,plic-1.0.0";145 reg = <0x0 0xc000000 0x0 0x4000000>;149 &cpu0_intc 0xffffffff150 &cpu1_intc 0xffffffff &cpu1_intc 9151 &cpu2_intc 0xffffffff &cpu2_intc 9152 &cpu3_intc 0xffffffff &cpu3_intc 9153 &cpu4_intc 0xffffffff &cpu4_intc 9>;[all …]
43 /* 128 MiB memory @ 0x0 */44 reg = <0x00000000 0x08000000>;48 vmmc: fixedregulator@0 {57 #clock-cells = <0>;63 #clock-cells = <0>;71 #clock-cells = <0>;79 #clock-cells = <0>;87 #clock-cells = <0>;95 #clock-cells = <0>;103 #clock-cells = <0>;[all …]
44 /* 128 MiB memory @ 0x0 */45 reg = <0x00000000 0x08000000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;86 #clock-cells = <0>;94 #clock-cells = <0>;102 #clock-cells = <0>;110 #clock-cells = <0>;118 #clock-cells = <0>;[all …]
47 reg = <0x10040000 0x1000>;53 #clock-cells = <0>;59 #size-cells = <0>;62 cpu: cpu@0 {64 reg = <0>;88 reg = <0x10000000 0x20000>;93 reg = <0x10001000 0x1000>;104 reg = <0x10002000 0x1000>;111 reg = <0x10003000 0x1000>;120 reg = <0x10004000 0x1000>;[all …]
45 * The PB11MPCore has 512 MiB memory @ 0x7000000046 * and the first 256 are also remapped @ 0x0000000048 reg = <0x70000000 0x20000000>;53 #size-cells = <0>;56 MP11_0: cpu@0 {59 reg = <0>;91 reg = <0x1f001000 0x1000>,92 <0x1f000100 0x100>;97 reg = <0x1f002000 0x1000>;99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,[all …]
14 reg = <0x0 0x70000000 0x0 0x800000>;17 ranges = <0x0 0x0 0x70000000 0x800000>;19 atf-sram@0 {20 reg = <0x0 0x20000>;26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */29 ranges = <0x0 0x0 0x00100000 0x1c000>;33 reg = <0x00004070 0x4>;36 ranges = <0x4070 0x4070 0x4>;41 reg = <0x00004074 0x4>;44 ranges = <0x4074 0x4074 0x4>;[all …]
66 #size-cells = <0>;85 cpu0: cpu@0 {88 reg = <0x000>;100 reg = <0x001>;113 reg = <0x200>;126 CPU_SLEEP_0: cpu-sleep-0 {132 arm,psci-suspend-param = <0x0010000>;135 CLUSTER_SLEEP_0: cluster-sleep-0 {141 arm,psci-suspend-param = <0x1010000>;154 #clock-cells = <0>;[all …]
