Searched +full:0 +full:x10010000 (Results 1 – 25 of 38) sorted by relevance
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/Linux-v5.15/Documentation/devicetree/bindings/clock/ |
D | samsung,exynos-clock.yaml | 57 reg = <0x10010000 0x30000>;
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D | exynos5410-clock.txt | 30 #clock-cells = <0>; 35 reg = <0x10010000 0x30000>; 46 reg = <0x12C00000 0x100>; 47 interrupts = <0 51 0>;
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/Linux-v5.15/drivers/gpu/drm/msm/dsi/ |
D | dsi_cfg.h | 11 #define MSM_DSI_VER_MAJOR_V2 0x02 12 #define MSM_DSI_VER_MAJOR_6G 0x03 13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000 14 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000 15 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001 16 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000 17 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000 18 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001 19 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001 20 #define MSM_DSI_6G_VER_MINOR_V1_4_2 0x10040002 [all …]
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/Linux-v5.15/Documentation/devicetree/bindings/serial/ |
D | sifive-serial.yaml | 61 reg = <0x10010000 0x1000>;
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/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/ |
D | ingenic,pinctrl.yaml | 18 which the pin is associated and N is an integer from 0 to 31 identifying the 32 pattern: "^pinctrl@[0-9a-f]+$" 68 const: 0 71 "^gpio@[0-9]$": 174 reg = <0x10010000 0x600>; 177 #size-cells = <0>; 179 gpio@0 { 181 reg = <0>; 184 gpio-ranges = <&pinctrl 0 0 32>;
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/Linux-v5.15/arch/mips/boot/dts/ingenic/ |
D | jz4740.dtsi | 12 #size-cells = <0>; 14 cpu0: cpu@0 { 16 compatible = "ingenic,xburst-mxu1.0"; 17 reg = <0>; 25 #address-cells = <0>; 33 reg = <0x10001000 0x14>; 44 #clock-cells = <0>; 49 #clock-cells = <0>; 55 reg = <0x10000000 0x100>; 65 reg = <0x10002000 0x1000>; [all …]
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D | x1000.dtsi | 13 #size-cells = <0>; 15 cpu0: cpu@0 { 17 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 18 reg = <0>; 26 #address-cells = <0>; 34 reg = <0x10001000 0x50>; 45 #clock-cells = <0>; 50 #clock-cells = <0>; 56 reg = <0x10000000 0x100>; 59 ranges = <0x0 0x10000000 0x100>; [all …]
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D | x1830.dtsi | 13 #size-cells = <0>; 15 cpu0: cpu@0 { 17 compatible = "ingenic,xburst-fpu2.0-mxu2.0"; 18 reg = <0>; 26 #address-cells = <0>; 34 reg = <0x10001000 0x50>; 45 #clock-cells = <0>; 50 #clock-cells = <0>; 56 reg = <0x10000000 0x100>; 59 ranges = <0x0 0x10000000 0x100>; [all …]
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D | jz4725b.dtsi | 12 #size-cells = <0>; 14 cpu0: cpu@0 { 16 compatible = "ingenic,xburst-mxu1.0"; 17 reg = <0>; 25 #address-cells = <0>; 33 reg = <0x10001000 0x14>; 44 #clock-cells = <0>; 49 #clock-cells = <0>; 55 reg = <0x10000000 0x100>; 65 reg = <0x10002000 0x1000>; [all …]
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D | jz4770.dtsi | 12 #size-cells = <0>; 14 cpu0: cpu@0 { 16 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 17 reg = <0>; 25 #address-cells = <0>; 33 reg = <0x10001000 0x40>; 44 #clock-cells = <0>; 49 #clock-cells = <0>; 55 reg = <0x10000000 0x100>; 58 ranges = <0x0 0x10000000 0x100>; [all …]
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D | jz4780.dtsi | 13 #size-cells = <0>; 15 cpu0: cpu@0 { 17 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 18 reg = <0>; 26 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 35 #address-cells = <0>; 43 reg = <0x10001000 0x50>; 54 #clock-cells = <0>; 59 #clock-cells = <0>; 65 reg = <0x10000000 0x100>; [all …]
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/Linux-v5.15/arch/arm/boot/dts/ |
D | mt7623n.dtsi | 22 reg = <0 0x13000000 0 0x200>; 29 reg = <0 0x13040000 0 0x30000>; 55 reg = <0 0x14000000 0 0x1000>; 62 reg = <0 0x14010000 0 0x1000>; 64 mediatek,larb-id = <0>; 74 reg = <0 0x16010000 0 0x1000>; 86 reg = <0 0x15001000 0 0x1000>; 99 reg = <0 0x15000000 0 0x1000>; 106 reg = <0 0x10205000 0 0x1000>; 117 reg = <0 0x15004000 0 0x1000>; [all …]
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D | versatile-ab.dts | 24 reg = <0x0 0x08000000>; 28 #clock-cells = <0>; 36 #size-cells = <0>; 40 #size-cells = <0>; 42 port@0 { 43 reg = <0>; 72 reg = <0x10000000 0x200>; 76 offset = <0x08>; 77 mask = <0x01>; 78 label = "versatile:0"; [all …]
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D | exynos5260.dtsi | 35 #size-cells = <0>; 63 cpu0: cpu@0 { 66 reg = <0x0>; 73 reg = <0x1>; 80 reg = <0x100>; 87 reg = <0x101>; 94 reg = <0x102>; 101 reg = <0x103>; 114 reg = <0x10010000 0x10000>; 120 reg = <0x10200000 0x10000>; [all …]
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D | exynos5410.dtsi | 31 #size-cells = <0>; 33 cpu0: cpu@0 { 36 reg = <0x0>; 43 reg = <0x1>; 50 reg = <0x2>; 57 reg = <0x3>; 70 reg = <0x10040000 0x5000>; 78 reg = <0x10010000 0x30000>; 84 reg = <0x03810000 0x0C>; 92 reg = <0x10060000 0x100>; [all …]
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D | arm-realview-eb.dtsi | 43 /* 128 MiB memory @ 0x0 */ 44 reg = <0x00000000 0x08000000>; 48 vmmc: fixedregulator@0 { 57 #clock-cells = <0>; 63 #clock-cells = <0>; 71 #clock-cells = <0>; 79 #clock-cells = <0>; 87 #clock-cells = <0>; 95 #clock-cells = <0>; 103 #clock-cells = <0>; [all …]
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D | ls1021a.dtsi | 74 #size-cells = <0>; 79 reg = <0xf00>; 80 clocks = <&clockgen 1 0>; 87 reg = <0xf01>; 88 clocks = <&clockgen 1 0>; 95 reg = <0x0 0x0 0x0 0x0>; 100 #clock-cells = <0>; 123 offset = <0xb0>; 124 mask = <0x02>; 137 reg = <0x0 0x1080000 0x0 0x1000>; [all …]
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D | arm-realview-pbx.dtsi | 44 /* 128 MiB memory @ 0x0 */ 45 reg = <0x00000000 0x08000000>; 66 #clock-cells = <0>; 72 #clock-cells = <0>; 78 #clock-cells = <0>; 86 #clock-cells = <0>; 94 #clock-cells = <0>; 102 #clock-cells = <0>; 110 #clock-cells = <0>; 118 #clock-cells = <0>; [all …]
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D | imx27.dtsi | 47 reg = <0x10040000 0x1000>; 53 #clock-cells = <0>; 59 #size-cells = <0>; 62 cpu: cpu@0 { 64 reg = <0>; 88 reg = <0x10000000 0x20000>; 93 reg = <0x10001000 0x1000>; 104 reg = <0x10002000 0x1000>; 111 reg = <0x10003000 0x1000>; 120 reg = <0x10004000 0x1000>; [all …]
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D | arm-realview-pb11mp.dts | 45 * The PB11MPCore has 512 MiB memory @ 0x70000000 46 * and the first 256 are also remapped @ 0x00000000 48 reg = <0x70000000 0x20000000>; 53 #size-cells = <0>; 56 MP11_0: cpu@0 { 59 reg = <0>; 91 reg = <0x1f001000 0x1000>, 92 <0x1f000100 0x100>; 97 reg = <0x1f002000 0x1000>; 99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, [all …]
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/Linux-v5.15/arch/riscv/boot/dts/sifive/ |
D | fu540-c000.dtsi | 24 #size-cells = <0>; 25 cpu0: cpu@0 { 31 reg = <0>; 144 compatible = "sifive,plic-1.0.0"; 145 reg = <0x0 0xc000000 0x0 0x4000000>; 149 &cpu0_intc 0xffffffff 150 &cpu1_intc 0xffffffff &cpu1_intc 9 151 &cpu2_intc 0xffffffff &cpu2_intc 9 152 &cpu3_intc 0xffffffff &cpu3_intc 9 153 &cpu4_intc 0xffffffff &cpu4_intc 9>; [all …]
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D | fu740-c000.dtsi | 24 #size-cells = <0>; 25 cpu0: cpu@0 { 32 reg = <0x0>; 56 reg = <0x1>; 80 reg = <0x2>; 104 reg = <0x3>; 128 reg = <0x4>; 145 #address-cells = <0>; 146 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 147 reg = <0x0 0xc000000 0x0 0x4000000>; [all …]
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/Linux-v5.15/arch/powerpc/boot/dts/ |
D | akebono.dts | 14 /memreserve/ 0x01f00000 0x00100000; // spin table 21 dcr-parent = <&{/cpus/cpu@0}>; 29 #size-cells = <0>; 31 cpu@0 { 34 reg = <0>; 59 cpu-release-addr = <0x0 0x01f00000>; 65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage 71 dcr-reg = <0xffc00000 0x00040000>; 72 #address-cells = <0>; 73 #size-cells = <0>; [all …]
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/Linux-v5.15/drivers/gpu/drm/radeon/ |
D | ni.c | 71 0x98fc, 72 0x98f0, 73 0x9834, 74 0x9838, 75 0x9870, 76 0x9874, 77 0x8a14, 78 0x8b24, 79 0x8bcc, 80 0x8b10, [all …]
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/Linux-v5.15/arch/arm/mach-davinci/ |
D | dm646x.c | 39 #define DAVINCI_VPIF_BASE (0x01C12000) 42 BIT_MASK(0)) 46 #define DM646X_EMAC_BASE 0x01c80000 47 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000) 48 #define DM646X_EMAC_CNTRL_OFFSET 0x0000 49 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000 50 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000 51 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000 109 .id = 0, 122 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) [all …]
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