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/Linux-v5.15/arch/arm/boot/dts/
Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
48 vmmc: fixedregulator@0 {
57 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
103 #clock-cells = <0>;
[all …]
Darm-realview-pbx.dtsi44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
102 #clock-cells = <0>;
110 #clock-cells = <0>;
118 #clock-cells = <0>;
[all …]
Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]
Darm-realview-pb11mp.dts45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
53 #size-cells = <0>;
56 MP11_0: cpu@0 {
59 reg = <0>;
91 reg = <0x1f001000 0x1000>,
92 <0x1f000100 0x100>;
97 reg = <0x1f002000 0x1000>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
Dmt7623.dtsi73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-mt8195.yaml126 reg = <0x10005000 0x1000>,
127 <0x11d10000 0x1000>,
128 <0x11d30000 0x1000>,
129 <0x11d40000 0x1000>,
130 <0x11e20000 0x1000>,
131 <0x11eb0000 0x1000>,
132 <0x11f40000 0x1000>,
133 <0x1000b000 0x1000>;
139 gpio-ranges = <&pio 0 0 144>;
141 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
Dpinctrl-mt8192.yaml129 reg = <0x10005000 0x1000>,
130 <0x11c20000 0x1000>,
131 <0x11d10000 0x1000>,
132 <0x11d30000 0x1000>,
133 <0x11d40000 0x1000>,
134 <0x11e20000 0x1000>,
135 <0x11e70000 0x1000>,
136 <0x11ea0000 0x1000>,
137 <0x11f20000 0x1000>,
138 <0x11f30000 0x1000>,
[all …]
Dmediatek,mt65xx-pinctrl.yaml68 '-[0-9]+$':
136 reg = <0 0x10005000 0 0x1000>;
141 reg = <0 0x1020C020 0 0x1000>;
146 reg = <0 0x1000B000 0 0x1000>;
157 i2c0_pins_a: i2c0-0 {
165 i2c1_pins_a: i2c1-0 {
173 i2c2_pins_a: i2c2-0 {
185 i2c3_pins_a: i2c3-0 {
Dmediatek,mt6779-pinctrl.yaml74 '-[0-9]*$':
115 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
116 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
117 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
120 enum: [0, 1, 2, 3]
126 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
127 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
128 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
131 enum: [0, 1, 2, 3]
152 reg = <0 0x10005000 0 0x1000>,
[all …]
Dmediatek,mt8183-pinctrl.yaml67 '-[0-9]+$':
118 When E1=0/E0=0, the strength is 0.125mA.
119 When E1=0/E0=1, the strength is 0.25mA.
120 When E1=1/E0=0, the strength is 0.5mA.
124 0: (E1, E0, EN) = (0, 0, 0)
125 1: (E1, E0, EN) = (0, 0, 1)
126 2: (E1, E0, EN) = (0, 1, 0)
127 3: (E1, E0, EN) = (0, 1, 1)
128 4: (E1, E0, EN) = (1, 0, 0)
129 5: (E1, E0, EN) = (1, 0, 1)
[all …]
/Linux-v5.15/arch/arm/include/debug/
Dimx-uart.h9 #define IMX1_UART1_BASE_ADDR 0x00206000
10 #define IMX1_UART2_BASE_ADDR 0x00207000
14 #define IMX21_UART1_BASE_ADDR 0x1000a000
15 #define IMX21_UART2_BASE_ADDR 0x1000b000
16 #define IMX21_UART3_BASE_ADDR 0x1000c000
17 #define IMX21_UART4_BASE_ADDR 0x1000d000
21 #define IMX25_UART1_BASE_ADDR 0x43f90000
22 #define IMX25_UART2_BASE_ADDR 0x43f94000
23 #define IMX25_UART3_BASE_ADDR 0x5000c000
24 #define IMX25_UART4_BASE_ADDR 0x50008000
[all …]
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8167.dtsi22 reg = <0 0x10000000 0 0x1000>;
28 reg = <0 0x10001000 0 0x1000>;
34 reg = <0 0x10018000 0 0x710>;
40 reg = <0 0x10006000 0 0x1000>;
46 #size-cells = <0>;
54 #power-domain-cells = <0>;
63 #power-domain-cells = <0>;
70 #power-domain-cells = <0>;
79 #size-cells = <0>;
86 #size-cells = <0>;
[all …]
Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
Dmt8516.dtsi21 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
[all …]
Dmt8192.dtsi20 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x000>;
50 reg = <0x100>;
61 reg = <0x200>;
72 reg = <0x300>;
83 reg = <0x400>;
94 reg = <0x500>;
[all …]
Dmt2712e.dtsi66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
154 #clock-cells = <0>;
[all …]
Dmt8173.dtsi136 #size-cells = <0>;
158 cpu0: cpu@0 {
161 reg = <0x000>;
176 reg = <0x001>;
191 reg = <0x100>;
206 reg = <0x101>;
221 CPU_SLEEP_0: cpu-sleep-0 {
227 arm,psci-suspend-param = <0x0010000>;
249 cpu_suspend = <0x84000001>;
250 cpu_off = <0x84000002>;
[all …]
Dmt8183.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x000>;
95 reg = <0x001>;
106 reg = <0x002>;
117 reg = <0x003>;
128 reg = <0x100>;
139 reg = <0x101>;
150 reg = <0x102>;
161 reg = <0x103>;
[all …]
/Linux-v5.15/arch/arm/mach-versatile/
Dversatile_dt.c25 #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
33 #define VERSATILE_SYS_PCICTL_OFFSET 0x44
34 #define VERSATILE_SYS_MCI_OFFSET 0x48
39 #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
40 #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
41 #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
46 #define VERSATILE_REFCLK 0
87 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data),
166 versatile_sys_base = of_iomap(np, 0); in versatile_dt_init()