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/Linux-v5.10/drivers/devfreq/event/
Drockchip-dfi.c26 #define DDRMON_CTRL 0x04
27 #define CLR_DDRMON_CTRL (0x1f0000 << 0)
28 #define LPDDR4_EN (0x10001 << 4)
29 #define HARDWARE_EN (0x10001 << 3)
30 #define LPDDR3_EN (0x10001 << 2)
31 #define SOFTWARE_EN (0x10001 << 1)
32 #define SOFTWARE_DIS (0x10000 << 1)
33 #define TIME_CNT_EN (0x10001 << 0)
35 #define DDRMON_CH0_COUNT_NUM 0x28
36 #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
[all …]
/Linux-v5.10/drivers/clk/axs10x/
Di2s_pll_clock.c22 #define PLL_IDIV_REG 0x0
23 #define PLL_FBDIV_REG 0x4
24 #define PLL_ODIV0_REG 0x8
25 #define PLL_ODIV1_REG 0xC
37 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
38 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
39 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
40 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
41 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
42 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/Linux-v5.10/drivers/gpu/drm/selftests/
Dtest-drm_plane_helper.c28 if (plane_state->src.x1 < 0) { in check_src_eq()
29 pr_err("src x coordinate %x should never be below 0.\n", plane_state->src.x1); in check_src_eq()
33 if (plane_state->src.y1 < 0) { in check_src_eq()
34 pr_err("src y coordinate %x should never be below 0.\n", plane_state->src.y1); in check_src_eq()
85 DRM_MODE("1024x768", 0, 65000, 1024, 1048, in igt_check_plane_state()
86 1184, 1344, 0, 768, 771, 777, 806, 0, in igt_check_plane_state()
101 set_src(&plane_state, 0, 0, fb.width << 16, fb.height << 16); in igt_check_plane_state()
102 set_crtc(&plane_state, 0, 0, fb.width, fb.height); in igt_check_plane_state()
107 FAIL(ret < 0, "Simple clipping check should pass\n"); in igt_check_plane_state()
109 FAIL_ON(!check_src_eq(&plane_state, 0, 0, 1024 << 16, 768 << 16)); in igt_check_plane_state()
[all …]
/Linux-v5.10/drivers/thermal/
Drockchip_thermal.c28 TSHUT_MODE_CRU = 0,
35 * 0: low active, 1: high active
38 TSHUT_LOW_ACTIVE = 0,
47 SENSOR_CPU = 0,
57 ADC_DECREMENT = 0,
88 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
89 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
151 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
152 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
179 #define TSADCV2_USER_CON 0x00
[all …]
/Linux-v5.10/drivers/media/platform/qcom/venus/
Dhfi_cmds.h12 #define HFI_CMD_SYS_INIT 0x10001
13 #define HFI_CMD_SYS_PC_PREP 0x10002
14 #define HFI_CMD_SYS_SET_RESOURCE 0x10003
15 #define HFI_CMD_SYS_RELEASE_RESOURCE 0x10004
16 #define HFI_CMD_SYS_SET_PROPERTY 0x10005
17 #define HFI_CMD_SYS_GET_PROPERTY 0x10006
18 #define HFI_CMD_SYS_SESSION_INIT 0x10007
19 #define HFI_CMD_SYS_SESSION_END 0x10008
20 #define HFI_CMD_SYS_SET_BUFFERS 0x10009
21 #define HFI_CMD_SYS_TEST_SSR 0x10101
[all …]
/Linux-v5.10/arch/x86/kvm/
Dpmu.h12 #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
14 #define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000
15 #define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001
16 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002
68 pmc->current_config = 0; in pmc_release_perf_event()
/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
Didle-states.yaml82 between 0 and infinite time, until a wake-up event occurs.
107 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
147 0| 1 time(ms)
152 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
332 #size-cells = <0>;
335 cpu@0 {
338 reg = <0x0 0x0>;
347 reg = <0x0 0x1>;
356 reg = <0x0 0x100>;
365 reg = <0x0 0x101>;
[all …]
/Linux-v5.10/lib/
Dtest_string.c16 for (i = 0; i < 256; i++) { in memset16_selftest()
17 for (j = 0; j < 256; j++) { in memset16_selftest()
18 memset(p, 0xa1, 256 * 2 * sizeof(v)); in memset16_selftest()
19 memset16(p + i, 0xb1b2, j); in memset16_selftest()
20 for (k = 0; k < 512; k++) { in memset16_selftest()
23 if (v != 0xa1a1) in memset16_selftest()
26 if (v != 0xb1b2) in memset16_selftest()
29 if (v != 0xa1a1) in memset16_selftest()
39 return (i << 24) | (j << 16) | k | 0x8000; in memset16_selftest()
40 return 0; in memset16_selftest()
[all …]
Dtest-kstrtox.c6 for (i = 0; i < ARRAY_SIZE(test); i++)
35 tmp = 0; \
37 if (rv >= 0) { \
50 const typeof(test[0]) *t = &test[i]; \
55 if (rv != 0) { \
56 WARN(1, "str '%s', base %u, expected 0/" fmt ", got %d\n", \
72 {"0", 10, 0ULL}, in test_kstrtoull_ok()
124 {"0x0", 16, 0x0ULL}, in test_kstrtoull_ok()
125 {"0x1", 16, 0x1ULL}, in test_kstrtoull_ok()
126 {"0x7f", 16, 0x7fULL}, in test_kstrtoull_ok()
[all …]
/Linux-v5.10/include/uapi/linux/
Ddlmconstants.h31 #define DLM_LOCK_NL 0 /* null */
46 * either return -EAGAIN from the dlm_lock call or will return 0 from
137 #define DLM_LKF_NOQUEUE 0x00000001
138 #define DLM_LKF_CANCEL 0x00000002
139 #define DLM_LKF_CONVERT 0x00000004
140 #define DLM_LKF_VALBLK 0x00000008
141 #define DLM_LKF_QUECVT 0x00000010
142 #define DLM_LKF_IVVALBLK 0x00000020
143 #define DLM_LKF_CONVDEADLK 0x00000040
144 #define DLM_LKF_PERSISTENT 0x00000080
[all …]
Dvboxguest.h17 #define VBG_IOCTL_HDR_VERSION 0x10001
19 #define VBG_IOCTL_HDR_TYPE_DEFAULT 0
56 #define VBG_IOC_VERSION 0x00010000u
86 /** The SVN revision of the driver, or 0. */
98 _IOWR('V', 0, struct vbg_ioctl_driver_version_info)
277 #define VBGL_IOC_AGC_FLAGS_CONFIG_ACQUIRE_MODE 0x00000001
278 #define VBGL_IOC_AGC_FLAGS_VALID_MASK 0x00000001
/Linux-v5.10/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/engine/
Dxtensa.c31 int c = 0; in nvkm_xtensa_oclass_get()
47 return nvkm_gpuobj_new(object->engine->subdev.device, 0x10000, align, in nvkm_xtensa_cclass_bind()
63 u32 unk104 = nvkm_rd32(device, base + 0xd04); in nvkm_xtensa_intr()
64 u32 intr = nvkm_rd32(device, base + 0xc20); in nvkm_xtensa_intr()
65 u32 chan = nvkm_rd32(device, base + 0xc28); in nvkm_xtensa_intr()
66 u32 unk10c = nvkm_rd32(device, base + 0xd0c); in nvkm_xtensa_intr()
68 if (intr & 0x10) in nvkm_xtensa_intr()
70 nvkm_wr32(device, base + 0xc20, intr); in nvkm_xtensa_intr()
71 intr = nvkm_rd32(device, base + 0xc20); in nvkm_xtensa_intr()
72 if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { in nvkm_xtensa_intr()
[all …]
/Linux-v5.10/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dsdio.h13 #define SDIOD_FBR_SIZE 0x100
16 #define SDIO_FUNC_ENABLE_1 0x02
17 #define SDIO_FUNC_ENABLE_2 0x04
20 #define SDIO_FUNC_READY_1 0x02
21 #define SDIO_FUNC_READY_2 0x04
24 #define INTR_STATUS_FUNC1 0x2
25 #define INTR_STATUS_FUNC2 0x4
28 #define REG_F0_REG_MASK 0x7FF
29 #define REG_F1_MISC_MASK 0x1FFFF
31 /* function 0 vendor specific CCCR registers */
[all …]
/Linux-v5.10/arch/mips/include/asm/netlogic/xlr/
Dfmn.h41 #define FMN_STNID_CPU0 0x00
42 #define FMN_STNID_CPU1 0x08
43 #define FMN_STNID_CPU2 0x10
44 #define FMN_STNID_CPU3 0x18
45 #define FMN_STNID_CPU4 0x20
46 #define FMN_STNID_CPU5 0x28
47 #define FMN_STNID_CPU6 0x30
48 #define FMN_STNID_CPU7 0x38
178 #define nlm_read_c2_status0() __read_32bit_c2_register($2, 0)
179 #define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v)
[all …]
/Linux-v5.10/include/linux/
Darm-smccc.h19 #define ARM_SMCCC_STD_CALL _AC(0,U)
23 #define ARM_SMCCC_SMC_32 0
27 #define ARM_SMCCC_OWNER_MASK 0x3F
30 #define ARM_SMCCC_FUNC_MASK 0xFFFF
46 #define ARM_SMCCC_OWNER_ARCH 0
58 #define ARM_SMCCC_QUIRK_NONE 0
61 #define ARM_SMCCC_VERSION_1_0 0x10000
62 #define ARM_SMCCC_VERSION_1_1 0x10001
63 #define ARM_SMCCC_VERSION_1_2 0x10002
68 0, 0)
[all …]
/Linux-v5.10/drivers/virt/vboxguest/
Dvmmdev.h17 #define VMMDEV_PORT_OFF_REQUEST 0
50 #define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED BIT(0)
72 #define VMMDEV_EVENT_VALID_EVENT_MASK 0x000007ffU
79 #define VMMDEV_VERSION 0x00010004
81 #define VMMDEV_VERSION_MINOR (VMMDEV_VERSION & 0xffff)
87 #define VMMDEV_REQUEST_HEADER_VERSION 0x10001
124 #define VMMDEV_MOUSE_GUEST_CAN_ABSOLUTE BIT(0)
155 #define VMMDEV_MOUSE_RANGE_MIN 0
157 #define VMMDEV_MOUSE_RANGE_MAX 0xFFFF
181 #define VMMDEV_HVF_HGCM_PHYS_PAGE_LIST BIT(0)
[all …]
/Linux-v5.10/sound/spi/
Dat73c213.c41 0x00, /* 00 - CTRL */
42 0x05, /* 01 - LLIG */
43 0x05, /* 02 - RLIG */
44 0x08, /* 03 - LPMG */
45 0x08, /* 04 - RPMG */
46 0x00, /* 05 - LLOG */
47 0x00, /* 06 - RLOG */
48 0x22, /* 07 - OLC */
49 0x09, /* 08 - MC */
50 0x00, /* 09 - CSFC */
[all …]
/Linux-v5.10/drivers/dma/
Dsirf-dma.c33 #define SIRFSOC_DMA_CH_ADDR 0x00
34 #define SIRFSOC_DMA_CH_XLEN 0x04
35 #define SIRFSOC_DMA_CH_YLEN 0x08
36 #define SIRFSOC_DMA_CH_CTRL 0x0C
38 #define SIRFSOC_DMA_WIDTH_0 0x100
39 #define SIRFSOC_DMA_CH_VALID 0x140
40 #define SIRFSOC_DMA_CH_INT 0x144
41 #define SIRFSOC_DMA_INT_EN 0x148
42 #define SIRFSOC_DMA_INT_EN_CLR 0x14C
43 #define SIRFSOC_DMA_CH_LOOP_CTRL 0x150
[all …]
/Linux-v5.10/drivers/mmc/host/
Dsdricoh_cs.c33 #define SDRICOH_PCI_REGION 0
34 #define SDRICOH_PCI_REGION_SIZE 0x1000
37 #define R104_VERSION 0x104
38 #define R200_CMD 0x200
39 #define R204_CMD_ARG 0x204
40 #define R208_DATAIO 0x208
41 #define R20C_RESP 0x20c
42 #define R21C_STATUS 0x21c
43 #define R2E0_INIT 0x2e0
44 #define R2E4_STATUS_RESP 0x2e4
[all …]
/Linux-v5.10/drivers/gpu/drm/panfrost/
Dpanfrost_regs.h11 #define GPU_ID 0x00
12 #define GPU_L2_FEATURES 0x004 /* (RO) Level 2 cache features */
13 #define GPU_CORE_FEATURES 0x008 /* (RO) Shader Core Features */
14 #define GPU_TILER_FEATURES 0x00C /* (RO) Tiler Features */
15 #define GPU_MEM_FEATURES 0x010 /* (RO) Memory system features */
16 #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */
18 #define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */
19 #define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */
20 #define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */
22 #define GPU_INT_RAWSTAT 0x20
[all …]
/Linux-v5.10/drivers/gpu/drm/radeon/
Drv515.c50 0,
75 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
81 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
83 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
85 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
86 radeon_ring_write(ring, 0); in rv515_ring_start()
87 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
88 radeon_ring_write(ring, 0); in rv515_ring_start()
89 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
91 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
[all …]
Drv770.c53 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
68 return 0; in rv770_set_uvd_clocks()
72 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
81 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
82 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
87 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
114 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
118 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
119 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/Linux-v5.10/drivers/media/pci/cx25821/
Dcx25821-medusa-video.c24 u32 value = 0; in medusa_enable_bluefield_output()
25 u32 tmp = 0; in medusa_enable_bluefield_output()
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
[all …]

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