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/Linux-v5.15/drivers/misc/habanalabs/include/goya/asic_reg/
Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/Linux-v5.15/drivers/misc/habanalabs/include/gaudi/asic_reg/
Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/Linux-v5.15/sound/soc/qcom/
Dlpass-sc7180.c82 int chan = 0; in sc7180_lpass_alloc_dma_channel()
122 return 0; in sc7180_lpass_free_dma_channel()
136 for (i = 0; i < drvdata->num_clks; i++) in sc7180_lpass_init()
151 return 0; in sc7180_lpass_init()
160 return 0; in sc7180_lpass_exit()
164 .i2sctrl_reg_base = 0x1000,
165 .i2sctrl_reg_stride = 0x1000,
167 .irq_reg_base = 0x9000,
168 .irq_reg_stride = 0x1000,
170 .rdma_reg_base = 0xC000,
[all …]
Dlpass-apq8016.c131 int chan = 0; in apq8016_lpass_alloc_dma_channel()
158 return 0; in apq8016_lpass_free_dma_channel()
175 for (i = 0; i < drvdata->num_clks; i++) in apq8016_lpass_init()
212 return 0; in apq8016_lpass_init()
226 return 0; in apq8016_lpass_exit()
231 .i2sctrl_reg_base = 0x1000,
232 .i2sctrl_reg_stride = 0x1000,
234 .irq_reg_base = 0x6000,
235 .irq_reg_stride = 0x1000,
237 .rdma_reg_base = 0x8400,
[all …]
/Linux-v5.15/arch/mips/boot/dts/ingenic/
Dx1000.dtsi3 #include <dt-bindings/clock/x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
9 compatible = "ingenic,x1000", "ingenic,x1000e";
13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
34 reg = <0x10001000 0x50>;
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dhisi-x5hd2.dtsi20 #address-cells = <0>;
23 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
31 ranges = <0 0xf8000000 0x8000000>;
41 reg = <0x00002000 0x1000>;
43 interrupts = <0 24 4>;
55 reg = <0x00a29000 0x1000>;
57 interrupts = <0 25 4>;
64 reg = <0x00a2a000 0x1000>;
66 interrupts = <0 26 4>;
73 reg = <0x00a2b000 0x1000>;
[all …]
Dnspire.dtsi14 cpu@0 {
19 bootrom: bootrom@0 {
20 reg = <0x00000000 0x80000>;
25 reg = <0xA4000000 0x20000>;
29 #clock-cells = <0>;
35 #clock-cells = <0>;
36 reg = <0x900B0024 0x4>;
40 #clock-cells = <0>;
41 reg = <0x900B0024 0x4>;
46 #clock-cells = <0>;
[all …]
Dqcom-apq8084.dtsi21 reg = <0xfa00000 0x200000>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
93 reg = <0x0 0x0>;
188 interrupts = <GIC_PPI 7 0xf04>;
194 #clock-cells = <0>;
200 #clock-cells = <0>;
207 interrupts = <GIC_PPI 2 0xf08>,
208 <GIC_PPI 3 0xf08>,
[all …]
Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt8192-clock.yaml57 reg = <0x10720000 0x1000>;
64 reg = <0x11007000 0x1000>;
71 reg = <0x11cb1000 0x1000>;
78 reg = <0x11d03000 0x1000>;
85 reg = <0x11d23000 0x1000>;
92 reg = <0x11e01000 0x1000>;
99 reg = <0x11f02000 0x1000>;
106 reg = <0x11f10000 0x1000>;
113 reg = <0x11f60000 0x1000>;
120 reg = <0x13fbf000 0x1000>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8183.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x000>;
95 reg = <0x001>;
106 reg = <0x002>;
117 reg = <0x003>;
128 reg = <0x100>;
139 reg = <0x101>;
150 reg = <0x102>;
161 reg = <0x103>;
[all …]
Dmt8173.dtsi136 #size-cells = <0>;
158 cpu0: cpu@0 {
161 reg = <0x000>;
176 reg = <0x001>;
191 reg = <0x100>;
206 reg = <0x101>;
221 CPU_SLEEP_0: cpu-sleep-0 {
227 arm,psci-suspend-param = <0x0010000>;
249 cpu_suspend = <0x84000001>;
250 cpu_off = <0x84000002>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/lg/
Dlg1312.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
57 cpu_suspend = <0x84000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0x84000003>;
66 reg = <0x0 0xc0001000 0x1000>,
[all …]
Dlg1313.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
57 cpu_suspend = <0x84000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0x84000003>;
66 reg = <0x0 0xc0001000 0x1000>,
[all …]
/Linux-v5.15/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
26 clocks = <&pmd0clk 0>;
31 reg = <0x0 0x001>;
33 cpu-release-addr = <0x1 0x0000fff8>;
36 clocks = <&pmd0clk 0>;
41 reg = <0x0 0x100>;
43 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/hisilicon/
Dhi3670.dtsi25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
68 reg = <0x0 0x1>;
75 reg = <0x0 0x2>;
82 reg = <0x0 0x3>;
89 reg = <0x0 0x100>;
96 reg = <0x0 0x101>;
103 reg = <0x0 0x102>;
110 reg = <0x0 0x103>;
[all …]
/Linux-v5.15/drivers/clk/sprd/
Dsc9860-clk.c26 6, 1, 0);
28 13, 1, 0);
30 26, 1, 0);
32 104, 1, 0);
34 1, 1, 0);
36 1, 1, 0);
38 4, 1, 0);
40 25, 1, 0);
42 50, 1, 0);
44 10, 1, 0);
[all …]
Dsc9863a-clk.c26 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
27 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
28 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
29 0x1000, BIT(0), 0, 0, 240);
30 static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
31 0x1000, BIT(0), 0, 0, 240);
32 static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
33 0x1000, BIT(0), 0, 0, 240);
34 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
35 0x1000, BIT(0), 0, 0, 240);
[all …]

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