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/Linux-v6.1/arch/sh/drivers/pci/
Dfixups-rts7751r2d.c17 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
18 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
48 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM); in pci_fixup_pcic()
49 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM); in pci_fixup_pcic()
51 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1); in pci_fixup_pcic()
52 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4); in pci_fixup_pcic()
58 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
59 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
60 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
[all …]
Dfixups-landisk.c18 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
19 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
29 int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0); in pcibios_map_platform_irq()
31 if ((slot | (pin - 1)) > 0x3) { in pcibios_map_platform_irq()
44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
51 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
52 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
53 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
54 pci_write_reg(chan, 0x00000000, SH4_PCILAR1); in pci_fixup_pcic()
56 return 0; in pci_fixup_pcic()
Dfixups-se7751.c14 case 0: return evt2irq(0x3a0); in pcibios_map_platform_irq()
15 case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */ in pcibios_map_platform_irq()
25 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
26 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
58 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ in pci_fixup_pcic()
61 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
72 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); in pci_fixup_pcic()
73 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); in pci_fixup_pcic()
76 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ in pci_fixup_pcic()
77 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ in pci_fixup_pcic()
[all …]
/Linux-v6.1/arch/powerpc/include/asm/
Dreg_a2.h13 #define SPRN_TENSR 0x1b5
14 #define SPRN_TENS 0x1b6 /* Thread ENable Set */
15 #define SPRN_TENC 0x1b7 /* Thread ENable Clear */
17 #define SPRN_A2_CCR0 0x3f0 /* Core Configuration Register 0 */
18 #define SPRN_A2_CCR1 0x3f1 /* Core Configuration Register 1 */
19 #define SPRN_A2_CCR2 0x3f2 /* Core Configuration Register 2 */
20 #define SPRN_MMUCR0 0x3fc /* MMU Control Register 0 */
21 #define SPRN_MMUCR1 0x3fd /* MMU Control Register 1 */
22 #define SPRN_MMUCR2 0x3fe /* MMU Control Register 2 */
23 #define SPRN_MMUCR3 0x3ff /* MMU Control Register 3 */
[all …]
/Linux-v6.1/arch/arm/mach-s3c/
Dbast.h16 #define BAST_CPLD_CTRL1_LRCOFF (0x00)
17 #define BAST_CPLD_CTRL1_LRCADC (0x01)
18 #define BAST_CPLD_CTRL1_LRCDAC (0x02)
19 #define BAST_CPLD_CTRL1_LRCARM (0x03)
20 #define BAST_CPLD_CTRL1_LRMASK (0x03)
24 #define BAST_CPLD_CTRL2_WNAND (0x04)
25 #define BAST_CPLD_CTLR2_IDERST (0x08)
29 #define BAST_CPLD_CTRL3_IDMASK (0x0e)
30 #define BAST_CPLD_CTRL3_ROMWEN (0x01)
34 #define BAST_CPLD_CTRL4_LLAT (0x01)
[all …]
Dvr1000.h14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
[all …]
/Linux-v6.1/arch/sh/include/mach-common/mach/
Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/
Dgamecube.dts24 reg = <0x00000000 0x01800000>;
29 #size-cells = <0>;
31 PowerPC,gekko@0 {
33 reg = <0>;
49 ranges = <0x0c000000 0x0c000000 0x00010000>;
54 reg = <0x0c002000 0x100>;
60 reg = <0x0c003000 0x100>;
73 reg = <0x0c005000 0x200>;
76 memory@0 {
78 reg = <0 0x1000000>; /* 16MB */
[all …]
Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/Linux-v6.1/arch/m68k/include/asm/
Dsun3mmu.h25 #define SUN3_CONTROL_MASK (0x0FFFFFFC)
29 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
30 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
31 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
32 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
33 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
34 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
35 #define AC_BUS_ERROR 0x60000000 /* 34 Cleared on read, byte. */
36 #define AC_SYNC_ERR 0x60000000 /* c fault type */
37 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
[all …]
/Linux-v6.1/drivers/net/ethernet/pasemi/
Dpasemi_mac.h110 PAS_MAC_CFG_PCFG = 0x80,
111 PAS_MAC_CFG_MACCFG = 0x84,
112 PAS_MAC_CFG_ADR0 = 0x8c,
113 PAS_MAC_CFG_ADR1 = 0x90,
114 PAS_MAC_CFG_TXP = 0x98,
115 PAS_MAC_CFG_RMON = 0x100,
116 PAS_MAC_IPC_CHNL = 0x208,
120 #define PAS_MAC_CFG_PCFG_PE 0x80000000
121 #define PAS_MAC_CFG_PCFG_CE 0x40000000
122 #define PAS_MAC_CFG_PCFG_BU 0x20000000
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dkeystone-k2e.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
64 reg = <0x2620750 24>;
72 reg = <0x25000000 0x10000>;
83 reg = <0x25010000 0x70000>;
91 reg = <0x0c000000 0x200000>;
92 ranges = <0x0 0x0c000000 0x200000>;
97 reg = <0x001f0000 0x8000>;
107 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
[all …]
/Linux-v6.1/arch/arm/mach-pxa/
Dtrizeps4.h22 #define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
27 #define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000)
29 #define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000)
31 #define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000)
33 #define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000)
36 #define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
38 #define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */
39 #define TRIZEPS4_CFSR_VIRT 0xF0100000
40 #define TRIZEPS4_BOCR_VIRT 0xF0200000
41 #define TRIZEPS4_DICR_VIRT 0xF0300000
[all …]
Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
/Linux-v6.1/arch/sh/include/cpu-sh4/cpu/
Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt47 Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
71 0x0 - MC portals
72 0x1 - QBMAN portals
99 have a value of 0.
154 stream-match-mask = <0x7C00>;
170 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
171 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
180 * Region type 0x0 - MC portals
181 * Region type 0x1 - QBMAN portals
183 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
[all …]
/Linux-v6.1/arch/sh/configs/
Dse7751_defconfig11 CONFIG_MEMORY_START=0x0c000000
Dse7705_defconfig11 CONFIG_MEMORY_START=0x0c000000
12 CONFIG_MEMORY_SIZE=0x02000000
Dse7750_defconfig13 CONFIG_MEMORY_START=0x0c000000
14 CONFIG_MEMORY_SIZE=0x02000000
Dse7619_defconfig13 CONFIG_MEMORY_START=0x0c000000
Drsk7269_defconfig9 CONFIG_MEMORY_START=0x0c000000
10 CONFIG_MEMORY_SIZE=0x02000000
Dsh7710voipgw_defconfig14 CONFIG_MEMORY_START=0x0c000000
15 CONFIG_MEMORY_SIZE=0x00800000
Dshmin_defconfig15 CONFIG_MEMORY_START=0x0c000000
16 CONFIG_MEMORY_SIZE=0x00800000
22 …onsole=ttySC1,115200 root=1f01 mtdparts=phys_mapped_flash:64k(firm)ro,-(sys) netdev=34,0x300,eth0 "
Dse7722_defconfig12 CONFIG_MEMORY_START=0x0c000000
Dlboxre2_defconfig10 CONFIG_MEMORY_START=0x0c000000

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