Home
last modified time | relevance | path

Searched +full:0 +full:x080 (Results 1 – 25 of 294) sorted by relevance

12345678910>>...12

/Linux-v5.15/sound/pci/oxygen/
Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/Linux-v5.15/sound/soc/codecs/
Dssm2602.h33 #define SSM2602_LINVOL 0x00
34 #define SSM2602_RINVOL 0x01
35 #define SSM2602_LOUT1V 0x02
36 #define SSM2602_ROUT1V 0x03
37 #define SSM2602_APANA 0x04
38 #define SSM2602_APDIGI 0x05
39 #define SSM2602_PWR 0x06
40 #define SSM2602_IFACE 0x07
41 #define SSM2602_SRATE 0x08
42 #define SSM2602_ACTIVE 0x09
[all …]
/Linux-v5.15/drivers/pinctrl/mediatek/
Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
Dpinctrl-mt8365.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
29 MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
30 MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
31 MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
32 MTK_PIN_DRV_GRP(3, 0x710, 0, 2),
33 MTK_PIN_DRV_GRP(4, 0x710, 4, 2),
34 MTK_PIN_DRV_GRP(5, 0x710, 4, 2),
35 MTK_PIN_DRV_GRP(6, 0x710, 4, 2),
[all …]
/Linux-v5.15/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
Dpinctrl-exynos-arm64.c24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
67 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
68 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
69 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
70 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
[all …]
/Linux-v5.15/drivers/net/ethernet/seeq/
Dsgiseeq.h35 #define SEEQ_RSTAT_OVERF 0x001 /* Overflow */
36 #define SEEQ_RSTAT_CERROR 0x002 /* CRC error */
37 #define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */
38 #define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */
39 #define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */
40 #define SEEQ_RSTAT_FIG 0x020 /* Frame is good */
41 #define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */
42 #define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
43 #define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */
44 #define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dfsl,xcvr.yaml90 reg = <0x30cc0000 0x800>,
91 <0x30cc0800 0x400>,
92 <0x30cc0c00 0x080>,
93 <0x30cc0e00 0x080>;
95 interrupts = <0x0 128 IRQ_TYPE_LEVEL_HIGH>;
101 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
103 resets = <&audiomix_reset 0>;
/Linux-v5.15/arch/mips/mm/
Dc-r3k.c40 *p = 0xa5a55a5a; in r3k_cache_size()
44 if (dummy != 0xa5a55a5a || (status & ST0_CM)) { in r3k_cache_size()
45 size = 0; in r3k_cache_size()
47 for (size = 128; size <= 0x40000; size <<= 1) in r3k_cache_size()
48 *(p + size) = 0; in r3k_cache_size()
51 (size <= 0x40000) && (*(p + size) == 0); in r3k_cache_size()
54 if (size > 0x40000) in r3k_cache_size()
55 size = 0; in r3k_cache_size()
75 for (i = 0; i < 128; i++) in r3k_cache_lsize()
76 *(p + i) = 0; in r3k_cache_lsize()
[all …]
Dpage-funcs.S26 * R4000 128 bytes S-cache: 0x058 bytes
27 * R4600 v1.7: 0x05c bytes
28 * R4600 v2.0: 0x060 bytes
29 * With prefetching, 16 word strides 0x120 bytes
42 * R4000 128 bytes S-cache: 0x11c bytes
43 * R4600 v1.7: 0x080 bytes
44 * R4600 v2.0: 0x07c bytes
45 * With prefetching, 16 word strides 0x540 bytes
/Linux-v5.15/drivers/phy/qualcomm/
Dphy-qcom-qmp.h11 #define QSERDES_PLL_BG_TIMER 0x00c
12 #define QSERDES_PLL_SSC_PER1 0x01c
13 #define QSERDES_PLL_SSC_PER2 0x020
14 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
15 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
18 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
19 #define QSERDES_PLL_CLK_ENABLE1 0x040
20 #define QSERDES_PLL_SYS_CLK_CTRL 0x044
[all …]
/Linux-v5.15/include/linux/spi/
Dmxs-spi.h19 #define HW_SSP_CTRL0 0x000
27 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
33 #define BP_SSP_CTRL0_XFER_COUNT 0
34 #define BM_SSP_CTRL0_XFER_COUNT 0xffff
35 #define HW_SSP_CMD0 0x010
41 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
43 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
44 #define BP_SSP_CMD0_CMD 0
45 #define BM_SSP_CMD0_CMD 0xff
46 #define HW_SSP_CMD1 0x020
[all …]
/Linux-v5.15/arch/arm/mach-omap1/
Dmmc.h7 #define OMAP1_MMC_SIZE 0x080
8 #define OMAP1_MMC1_BASE 0xfffb7800
9 #define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
/Linux-v5.15/arch/sparc/lib/
Dbzero.S14 and %o1, 0xff, %o3
30 prefetch [%o0 + 0x000], #n_writes
31 andcc %o0, 0x3, %g0
33 1: stb %o2, [%o0 + 0x00]
35 andcc %o0, 0x3, %g0
38 2: andcc %o0, 0x7, %g0
40 stw %o2, [%o0 + 0x00]
43 3: and %o1, 0x38, %g1
44 cmp %o1, 0x40
45 andn %o1, 0x3f, %o4
[all …]
/Linux-v5.15/drivers/video/fbdev/riva/
Driva_hw.h50 #define RIVA_SW_VERSION 0x00010003
60 #define FALSE 0
63 #define NULL 0
91 #define NV_ARCH_03 0x03
92 #define NV_ARCH_04 0x04
93 #define NV_ARCH_10 0x10
94 #define NV_ARCH_20 0x20
95 #define NV_ARCH_30 0x30
96 #define NV_ARCH_40 0x40
116 U032 reserved01[0x0BB];
[all …]
/Linux-v5.15/arch/sh/include/mach-dreamcast/mach/
Dmaple.h11 MAPLE_DMA_ORDER - PAGE_SHIFT : 0)
14 #define MAPLE_BASE 0xa05f6c00
15 #define MAPLE_DMAADDR (MAPLE_BASE+0x04)
16 #define MAPLE_TRIGTYPE (MAPLE_BASE+0x10)
17 #define MAPLE_ENABLE (MAPLE_BASE+0x14)
18 #define MAPLE_STATE (MAPLE_BASE+0x18)
19 #define MAPLE_SPEED (MAPLE_BASE+0x80)
20 #define MAPLE_RESET (MAPLE_BASE+0x8c)
22 #define MAPLE_MAGIC 0x6155404f
23 #define MAPLE_2MBPS 0
[all …]
/Linux-v5.15/arch/parisc/include/uapi/asm/
Dtermios.h26 #define TIOCM_LE 0x001
27 #define TIOCM_DTR 0x002
28 #define TIOCM_RTS 0x004
29 #define TIOCM_ST 0x008
30 #define TIOCM_SR 0x010
31 #define TIOCM_CTS 0x020
32 #define TIOCM_CAR 0x040
33 #define TIOCM_RNG 0x080
34 #define TIOCM_DSR 0x100
37 #define TIOCM_OUT1 0x2000
[all …]
/Linux-v5.15/arch/s390/include/uapi/asm/
Dtermios.h32 #define TIOCM_LE 0x001
33 #define TIOCM_DTR 0x002
34 #define TIOCM_RTS 0x004
35 #define TIOCM_ST 0x008
36 #define TIOCM_SR 0x010
37 #define TIOCM_CTS 0x020
38 #define TIOCM_CAR 0x040
39 #define TIOCM_RNG 0x080
40 #define TIOCM_DSR 0x100
43 #define TIOCM_OUT1 0x2000
[all …]
/Linux-v5.15/arch/ia64/include/uapi/asm/
Dtermios.h33 #define TIOCM_LE 0x001
34 #define TIOCM_DTR 0x002
35 #define TIOCM_RTS 0x004
36 #define TIOCM_ST 0x008
37 #define TIOCM_SR 0x010
38 #define TIOCM_CTS 0x020
39 #define TIOCM_CAR 0x040
40 #define TIOCM_RNG 0x080
41 #define TIOCM_DSR 0x100
44 #define TIOCM_OUT1 0x2000
[all …]
/Linux-v5.15/include/uapi/asm-generic/
Dtermios.h33 #define TIOCM_LE 0x001
34 #define TIOCM_DTR 0x002
35 #define TIOCM_RTS 0x004
36 #define TIOCM_ST 0x008
37 #define TIOCM_SR 0x010
38 #define TIOCM_CTS 0x020
39 #define TIOCM_CAR 0x040
40 #define TIOCM_RNG 0x080
41 #define TIOCM_DSR 0x100
44 #define TIOCM_OUT1 0x2000
[all …]
/Linux-v5.15/arch/arm64/boot/dts/hisilicon/
Dhikey970-pinctrl.dtsi16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7603/
Deeprom.h9 MT_EE_CHIP_ID = 0x000,
10 MT_EE_VERSION = 0x002,
11 MT_EE_MAC_ADDR = 0x004,
12 MT_EE_NIC_CONF_0 = 0x034,
13 MT_EE_NIC_CONF_1 = 0x036,
14 MT_EE_NIC_CONF_2 = 0x042,
16 MT_EE_XTAL_TRIM_1 = 0x03a,
18 MT_EE_RSSI_OFFSET_2G = 0x046,
19 MT_EE_WIFI_RF_SETTING = 0x048,
20 MT_EE_RSSI_OFFSET_5G = 0x04a,
[all …]
/Linux-v5.15/arch/arm/mach-pxa/include/mach/
Dlubbock.h15 #define LUBBOCK_FPGA_VIRT (0xf0000000)
26 #define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
27 #define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
28 #define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
29 #define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
30 #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
31 #define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
32 #define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
33 #define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
34 #define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
[all …]
/Linux-v5.15/drivers/clk/mediatek/
Dclk-mt7622.c295 .set_ofs = 0x8,
296 .clr_ofs = 0x8,
297 .sta_ofs = 0x8,
301 .set_ofs = 0x40,
302 .clr_ofs = 0x44,
303 .sta_ofs = 0x48,
307 .set_ofs = 0x120,
308 .clr_ofs = 0x120,
309 .sta_ofs = 0x120,
313 .set_ofs = 0x128,
[all …]

12345678910>>...12