| /Linux-v6.1/drivers/net/wireless/realtek/rtw88/ |
| D | rtw8822b_table.c | 10 0x029, 0x000000F9,
11 0x420, 0x00000080,
12 0x421, 0x0000001F,
13 0x428, 0x0000000A,
14 0x429, 0x00000010,
15 0x430, 0x00000000,
16 0x431, 0x00000000,
17 0x432, 0x00000000,
18 0x433, 0x00000001,
19 0x434, 0x00000004,
[all …]
|
| D | rtw8723d_table.c | 10 0x020, 0x00000013,
11 0x02F, 0x00000010,
12 0x077, 0x00000007,
13 0x421, 0x0000000F,
14 0x428, 0x0000000A,
15 0x429, 0x00000010,
16 0x430, 0x00000000,
17 0x431, 0x00000000,
18 0x432, 0x00000000,
19 0x433, 0x00000001,
[all …]
|
| D | rtw8822c_table.c | 16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]
|
| D | rtw8821c_table.c | 10 0x010, 0x00000043,
11 0x025, 0x0000001D,
12 0x026, 0x000000CE,
13 0x04F, 0x00000001,
14 0x029, 0x000000F9,
15 0x420, 0x00000080,
16 0x421, 0x0000001F,
17 0x428, 0x0000000A,
18 0x429, 0x00000010,
19 0x430, 0x00000000,
[all …]
|
| /Linux-v6.1/sound/pci/oxygen/ |
| D | wm8776.h | 14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
|
| D | wm8766.h | 5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
|
| /Linux-v6.1/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt8195.c | 13 * iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000,
14 * iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000,
15 * iocfg[6]:0x11f40000.
21 32, 0)
28 PIN_FIELD(0, 144, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 144, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 144, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 144, 0x100, 0x10, 0, 1),
44 PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1),
45 PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1),
[all …]
|
| /Linux-v6.1/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-qserdes-txrx-v3.h | 10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
|
| D | phy-qcom-qmp-qserdes-txrx.h | 10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
|
| D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
|
| D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
|
| D | phy-qcom-qmp-pcs-ufs-v5.h | 11 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
12 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
13 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
14 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
15 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
16 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
17 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
18 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
19 #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
20 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
[all …]
|
| D | phy-qcom-qmp-pcs-ufs-v4.h | 10 #define QPHY_V4_PCS_UFS_PHY_START 0x000
11 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V4_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
16 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
|
| D | phy-qcom-qmp-pcs-usb-v5.h | 10 #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
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| D | phy-qcom-qmp-pcs-usb-v4.h | 10 #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
|
| /Linux-v6.1/drivers/net/wireless/realtek/rtw89/ |
| D | rtw8852c_table.c | 10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0x70C, 0x00000020},
14 {0x704, 0x601E0100},
15 {0x4000, 0x00000000},
16 {0x4004, 0xCA014000},
17 {0x4008, 0xC751D4F0},
18 {0x400C, 0x44511475},
19 {0x4010, 0x00000000},
[all …]
|
| /Linux-v6.1/drivers/clk/mediatek/ |
| D | clk-mt7986-topckgen.c | 178 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
180 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
182 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
184 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
187 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
189 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
190 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
|
| /Linux-v6.1/arch/arm64/boot/dts/hisilicon/ |
| D | hikey970-pinctrl.dtsi | 16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
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| /Linux-v6.1/arch/mips/include/asm/ |
| D | mips-cpc.h | 33 * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
60 #define MIPS_CPC_GCB_OFS 0x0000
61 #define MIPS_CPC_CLCB_OFS 0x2000
62 #define MIPS_CPC_COCB_OFS 0x4000
81 CPC_ACCESSOR_RW(32, 0x000, access)
84 CPC_ACCESSOR_RW(32, 0x008, seqdel)
87 CPC_ACCESSOR_RW(32, 0x010, rail)
90 CPC_ACCESSOR_RW(32, 0x018, resetlen)
93 CPC_ACCESSOR_RO(32, 0x020, revision)
96 CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
[all …]
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| /Linux-v6.1/drivers/media/platform/ti/omap3isp/ |
| D | ispreg.h | 21 #define ISP_REVISION (0x000)
22 #define ISP_SYSCONFIG (0x004)
23 #define ISP_SYSSTATUS (0x008)
24 #define ISP_IRQ0ENABLE (0x00C)
25 #define ISP_IRQ0STATUS (0x010)
26 #define ISP_IRQ1ENABLE (0x014)
27 #define ISP_IRQ1STATUS (0x018)
28 #define ISP_TCTRL_GRESET_LENGTH (0x030)
29 #define ISP_TCTRL_PSTRB_REPLAY (0x034)
30 #define ISP_CTRL (0x040)
[all …]
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| /Linux-v6.1/drivers/media/platform/mediatek/mdp3/ |
| D | mdp_reg_ccorr.h | 10 #define MDP_CCORR_EN 0x000
11 #define MDP_CCORR_CFG 0x020
12 #define MDP_CCORR_SIZE 0x030
15 #define MDP_CCORR_EN_MASK 0x00000001
16 #define MDP_CCORR_CFG_MASK 0x70001317
17 #define MDP_CCORR_SIZE_MASK 0x1fff1fff
|
| D | mdp_reg_rsz.h | 10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
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| /Linux-v6.1/drivers/soc/mediatek/ |
| D | mt8167-mmsys.h | 6 #define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030
7 #define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038
8 #define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058
9 #define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0x064
10 #define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06c
12 #define MT8167_DITHER_MOUT_EN_RDMA0 0x1
13 #define MT8167_RDMA0_SOUT_DSI0 0x2
14 #define MT8167_DSI0_SEL_IN_RDMA0 0x1
|
| /Linux-v6.1/drivers/rtc/ |
| D | rtc-gamecube.c | 12 * This device sits on a bus named EXI (which is similar to SPI), channel 0,
40 #define EXICSR 0
45 #define EXICSR_DEV 0x380
46 #define EXICSR_DEV1 0x100
47 #define EXICSR_CLK 0x070
48 #define EXICSR_CLK_1MHZ 0x000
49 #define EXICSR_CLK_2MHZ 0x010
50 #define EXICSR_CLK_4MHZ 0x020
51 #define EXICSR_CLK_8MHZ 0x030
52 #define EXICSR_CLK_16MHZ 0x040
[all …]
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| /Linux-v6.1/arch/arm/mach-versatile/ |
| D | v2m.c | 8 #define SYS_FLAGSSET 0x030
9 #define SYS_FLAGSCLR 0x034
19 base = of_iomap(node, 0); in vexpress_flags_set()
25 writel(~0, base + SYS_FLAGSCLR); in vexpress_flags_set()
36 .l2c_aux_val = 0x00400000,
37 .l2c_aux_mask = 0xfe0fffff,
|
