Home
last modified time | relevance | path

Searched +full:0 +full:x02000 (Results 1 – 25 of 73) sorted by relevance

123

/Linux-v5.15/drivers/mtd/chips/
Djedec_probe.c26 #define AM29DL800BB 0x22CB
27 #define AM29DL800BT 0x224A
29 #define AM29F800BB 0x2258
30 #define AM29F800BT 0x22D6
31 #define AM29LV400BB 0x22BA
32 #define AM29LV400BT 0x22B9
33 #define AM29LV800BB 0x225B
34 #define AM29LV800BT 0x22DA
35 #define AM29LV160DT 0x22C4
36 #define AM29LV160DB 0x2249
[all …]
/Linux-v5.15/drivers/gpu/drm/nouveau/
Dnouveau_chan.c80 return 0; in nouveau_channel_idle()
128 if (ret == 0) { in nouveau_channel_wait()
154 atomic_set(&chan->killed, 0); in nouveau_channel_prep()
161 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, in nouveau_channel_prep()
163 if (ret == 0) { in nouveau_channel_prep()
165 if (ret == 0) in nouveau_channel_prep()
199 return 0; in nouveau_channel_prep()
203 args.start = 0; in nouveau_channel_prep()
220 args.start = 0; in nouveau_channel_prep()
233 args.start = 0; in nouveau_channel_prep()
[all …]
/Linux-v5.15/tools/arch/alpha/include/uapi/asm/
Dmman.h13 #define MADV_NORMAL 0
19 #define MAP_ANONYMOUS 0x10
20 #define MAP_DENYWRITE 0x02000
21 #define MAP_EXECUTABLE 0x04000
22 #define MAP_FILE 0
23 #define MAP_FIXED 0x100
24 #define MAP_GROWSDOWN 0x01000
25 #define MAP_HUGETLB 0x100000
26 #define MAP_LOCKED 0x08000
27 #define MAP_NONBLOCK 0x40000
[all …]
/Linux-v5.15/arch/alpha/include/asm/
Dsetup.h12 #define BOOT_PCB 0x20000000
13 #define BOOT_ADDR 0x20000000
18 #define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
20 #define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
25 #define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
26 #define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
27 #define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
28 #define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
30 #define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
39 #define COMMAND_LINE ((char *)(absolute_pointer(PARAM + 0x0000)))
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/i3c/
Dsnps,dw-i3c-master.txt15 - #size-cells: shall be set to 0
31 #size-cells = <0>;
32 reg = <0x02000 0x1000>;
33 interrupts = <0>;
38 reg = <0x57 0x0 0x10>;
39 pagesize = <0x8>;
/Linux-v5.15/drivers/net/ethernet/intel/ixgbevf/
Dregs.h7 #define IXGBE_VFCTRL 0x00000
8 #define IXGBE_VFSTATUS 0x00008
9 #define IXGBE_VFLINKS 0x00010
10 #define IXGBE_VFFRTIMER 0x00048
11 #define IXGBE_VFRXMEMWRAP 0x03190
12 #define IXGBE_VTEICR 0x00100
13 #define IXGBE_VTEICS 0x00104
14 #define IXGBE_VTEIMS 0x00108
15 #define IXGBE_VTEIMC 0x0010C
16 #define IXGBE_VTEIAC 0x00110
[all …]
/Linux-v5.15/arch/mips/include/asm/netlogic/xlr/
Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/Linux-v5.15/arch/alpha/include/uapi/asm/
Dmman.h5 #define PROT_READ 0x1 /* page can be read */
6 #define PROT_WRITE 0x2 /* page can be written */
7 #define PROT_EXEC 0x4 /* page can be executed */
8 #define PROT_SEM 0x8 /* page may be used for atomic ops */
9 #define PROT_NONE 0x0 /* page can not be accessed */
10 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
11 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
13 /* 0x01 - 0x03 are defined in linux/mman.h */
14 #define MAP_TYPE 0x0f /* Mask for type of mapping (OSF/1 is _wrong_) */
15 #define MAP_FIXED 0x100 /* Interpret addr exactly */
[all …]
/Linux-v5.15/arch/arm/mach-imx/
Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/Linux-v5.15/arch/mips/include/asm/mach-ar7/
Dar7.h16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]
/Linux-v5.15/drivers/pci/controller/
Dpcie-rcar.h12 #define PCIECAR 0x000010
13 #define PCIECCTLR 0x000018
15 #define TYPE0 (0 << 8)
17 #define PCIECDR 0x000020
18 #define PCIEMSR 0x000028
19 #define PCIEINTXR 0x000400
21 #define PCIEPHYSR 0x0007f0
22 #define PHYRDY BIT(0)
23 #define PCIEMSITXR 0x000840
26 #define PCIETCTLR 0x02000
[all …]
/Linux-v5.15/arch/mips/include/asm/sgi/
Dhpc3.h22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
[all …]
/Linux-v5.15/drivers/gpu/drm/lima/
Dlima_device.c51 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
52 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
53 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
54 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
55 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
56 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
57 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
58 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
59 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
60 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
[all …]
/Linux-v5.15/drivers/net/wireless/ti/wl18xx/
Dreg.h11 #define WL18XX_REGISTERS_BASE 0x00800000
12 #define WL18XX_CODE_BASE 0x00000000
13 #define WL18XX_DATA_BASE 0x00400000
14 #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000
15 #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000
16 #define WL18XX_PHY_BASE 0x00900000
17 #define WL18XX_TOP_OCP_BASE 0x00A00000
18 #define WL18XX_PACKET_RAM_BASE 0x00B00000
19 #define WL18XX_HOST_BASE 0x00C00000
21 #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000
[all …]
/Linux-v5.15/arch/arm/mach-ux500/
Ddb8500-regs.h10 #define U8500_ESRAM_BASE 0x40000000
11 #define U8500_ESRAM_BANK_SIZE 0x00020000
21 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
28 #define U8500_PER3_BASE 0x80000000
29 #define U8500_STM_BASE 0x80100000
30 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
31 #define U8500_PER2_BASE 0x80110000
32 #define U8500_PER1_BASE 0x80120000
33 #define U8500_B2R2_BASE 0x80130000
34 #define U8500_HSEM_BASE 0x80140000
[all …]
/Linux-v5.15/drivers/video/fbdev/i810/
Di810_regs.h33 #define FENCE 0x02000
34 #define PGTBL_CTL 0x02020
35 #define PGTBL_ER 0x02024
36 #define LRING 0x02030
37 #define IRING 0x02040
38 #define HWS_PGA 0x02080
39 #define IPEIR 0x02088
40 #define IPEHR 0x0208C
41 #define INSTDONE 0x02090
42 #define NOPID 0x02094
[all …]
/Linux-v5.15/drivers/clk/spear/
Dspear1340_clock.c23 #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
30 #define SPEAR1340_PLL_CFG (misc_base + 0x210)
42 #define SPEAR1340_PLL1_CTR (misc_base + 0x214)
43 #define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
44 #define SPEAR1340_PLL2_CTR (misc_base + 0x220)
45 #define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
46 #define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
47 #define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
48 #define SPEAR1340_PLL4_CTR (misc_base + 0x238)
49 #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
[all …]
/Linux-v5.15/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi5_core.h16 #define HDMI_CORE_DESIGN_ID 0x00000
17 #define HDMI_CORE_REVISION_ID 0x00004
18 #define HDMI_CORE_PRODUCT_ID0 0x00008
19 #define HDMI_CORE_PRODUCT_ID1 0x0000C
20 #define HDMI_CORE_CONFIG0_ID 0x00010
21 #define HDMI_CORE_CONFIG1_ID 0x00014
22 #define HDMI_CORE_CONFIG2_ID 0x00018
23 #define HDMI_CORE_CONFIG3_ID 0x0001C
26 #define HDMI_CORE_IH_FC_STAT0 0x00400
27 #define HDMI_CORE_IH_FC_STAT1 0x00404
[all …]
/Linux-v5.15/drivers/gpu/drm/omapdrm/dss/
Dhdmi5_core.h16 #define HDMI_CORE_DESIGN_ID 0x00000
17 #define HDMI_CORE_REVISION_ID 0x00004
18 #define HDMI_CORE_PRODUCT_ID0 0x00008
19 #define HDMI_CORE_PRODUCT_ID1 0x0000C
20 #define HDMI_CORE_CONFIG0_ID 0x00010
21 #define HDMI_CORE_CONFIG1_ID 0x00014
22 #define HDMI_CORE_CONFIG2_ID 0x00018
23 #define HDMI_CORE_CONFIG3_ID 0x0001C
26 #define HDMI_CORE_IH_FC_STAT0 0x00400
27 #define HDMI_CORE_IH_FC_STAT1 0x00404
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7915/
Dmmio.c37 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ in __mt7915_reg_addr()
38 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ in __mt7915_reg_addr()
39 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ in __mt7915_reg_addr()
40 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ in __mt7915_reg_addr()
41 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ in __mt7915_reg_addr()
42 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ in __mt7915_reg_addr()
43 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ in __mt7915_reg_addr()
44 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ in __mt7915_reg_addr()
45 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ in __mt7915_reg_addr()
46 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ in __mt7915_reg_addr()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml66 enum: [ 0, 1 ]
73 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
77 SPI interrupts are in the range [0-987]. PPI interrupts are in the
78 range [0-15].
81 bits[3:0] trigger type and level flags.
149 "^v2m@[0-9a-f]+$":
196 reg = <0xfff11000 0x1000>,
197 <0xfff10100 0x100>;
206 reg = <0x2c001000 0x1000>,
207 <0x2c002000 0x2000>,
[all …]
/Linux-v5.15/drivers/memstick/host/
Dtifm_ms.c29 #define TIFM_MS_STAT_DRQ 0x04000
30 #define TIFM_MS_STAT_MSINT 0x02000
31 #define TIFM_MS_STAT_RDY 0x01000
32 #define TIFM_MS_STAT_CRC 0x00200
33 #define TIFM_MS_STAT_TOE 0x00100
34 #define TIFM_MS_STAT_EMP 0x00020
35 #define TIFM_MS_STAT_FUL 0x00010
36 #define TIFM_MS_STAT_CED 0x00008
37 #define TIFM_MS_STAT_ERR 0x00004
38 #define TIFM_MS_STAT_BRQ 0x00002
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7615/
Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/Linux-v5.15/arch/arm/kernel/
Datags_compat.c42 unsigned long page_size; /* 0 */
104 if (params->u1.s.nr_pages != 0x02000 && in build_tag_list()
105 params->u1.s.nr_pages != 0x04000 && in build_tag_list()
106 params->u1.s.nr_pages != 0x08000 && in build_tag_list()
107 params->u1.s.nr_pages != 0x10000) { in build_tag_list()
110 params->u1.s.nr_pages = 0x1000; /* 16MB */ in build_tag_list()
111 params->u1.s.ramdisk_size = 0; in build_tag_list()
113 params->u1.s.initrd_start = 0; in build_tag_list()
114 params->u1.s.initrd_size = 0; in build_tag_list()
115 params->u1.s.rd_start = 0; in build_tag_list()
[all …]
/Linux-v5.15/drivers/usb/gadget/udc/
Dgoku_udc.h12 * PCI BAR 0 points to these registers.
16 u32 int_status; /* 0x000 */
18 #define INT_SUSPEND 0x00001 /* or resume */
19 #define INT_USBRESET 0x00002
20 #define INT_ENDPOINT0 0x00004
21 #define INT_SETUP 0x00008
22 #define INT_STATUS 0x00010
23 #define INT_STATUSNAK 0x00020
24 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
25 # define INT_EP1DATASET 0x00040
[all …]

123