Searched +full:0 +full:x01d00000 (Results 1 – 15 of 15) sorted by relevance
42 alchemy_gpio_direction_output(4, 0); in gpr_reset()43 alchemy_gpio_direction_output(5, 0); in gpr_reset()48 alchemy_gpio_direction_output(1, 0); in gpr_reset()81 [0] = {91 .id = 0,99 * 0x00000000-0x00200000 : "kernel"100 * 0x00200000-0x00a00000 : "rootfs"101 * 0x01d00000-0x01f00000 : "config"102 * 0x01c00000-0x01d00000 : "yamon"103 * 0x01d00000-0x01d40000 : "yamon env vars"[all …]
19 memory@0 {21 reg = <0x00000000 0x08000000>,22 <0x88000000 0x08000000>;27 reg = <0x1c080000 0x100000>;83 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;136 reg = <0x200>;138 #size-cells = <0>;140 switch@0 {143 #size-cells = <0>;146 reg = <0>;[all …]
72 #size-cells = <0>;74 cpu0: cpu@0 {77 reg = <0>;155 reg = <0x01400000 0x20000>;168 reg = <0x01c00000 0x1000>;175 reg = <0x01d00000 0x80000>;178 ranges = <0 0x01d00000 0x80000>;180 ve_sram: sram-section@0 {183 reg = <0x000000 0x80000>;190 reg = <0x01c0e000 0x1000>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
91 #size-cells = <0>;93 cpu0: cpu@0 {96 reg = <0>;112 #clock-cells = <0>;120 #clock-cells = <0>;136 reg = <0x01c00000 0x30>;143 reg = <0x01d00000 0x80000>;146 ranges = <0 0x01d00000 0x80000>;148 ve_sram: sram-section@0 {151 reg = <0x000000 0x80000>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
64 #clock-cells = <0>;72 #clock-cells = <0>;82 #size-cells = <0>;84 cpu0: cpu@0 {87 reg = <0>;130 polling-delay-passive = <0>;131 polling-delay = <0>;132 thermal-sensors = <&ths 0>;143 hysteresis = <0>;161 polling-delay-passive = <0>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
9 #define DAVINCI_ASP0_BASE 0x01E0200010 #define DAVINCI_ASP1_BASE 0x01E0400013 #define DAVINCI_DM365_ASP0_BASE 0x01D0200016 #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D0100017 #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D0180020 #define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D0000023 #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D0400026 #define DAVINCI_DA830_MCASP2_REG_BASE 0x01D0800040 #define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
23 #define DAVINCI_I2C_BASE 0x01C2100024 #define DAVINCI_ATA_BASE 0x01C6600025 #define DAVINCI_MMCSD0_BASE 0x01E1000026 #define DM355_MMCSD0_BASE 0x01E1100027 #define DM355_MMCSD1_BASE 0x01E0000028 #define DM365_MMCSD0_BASE 0x01D1100029 #define DM365_MMCSD1_BASE 0x01D0000036 0x800); in davinci_map_sysmod()48 .end = DAVINCI_I2C_BASE + 0x40,76 .end = DAVINCI_ATA_BASE + 0x7ff,[all …]
105 reg = <0x01d00000 0xff000>;
22 gpios = <&gpt2 0 1>;25 gpios = <&gpt3 0 1>;34 memory@0 {35 reg = <0x00000000 0x10000000>; // 256MB41 cell-index = <0>;87 phy0: ethernet-phy@0 {88 reg = <0>;95 reg = <0x50>;101 reg = <0x8000 0x4000>;106 interrupt-map-mask = <0xf800 0 0 7>;[all …]
23 memory@0 {24 reg = <0x00000000 0x08000000>; // 128MB30 cell-index = <0>;61 phy0: ethernet-phy@0 {62 reg = <0>;69 reg = <0x51>;73 reg = <0x52>;80 interrupt-map-mask = <0xf800 0 0 7>;81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot82 0xc000 0 0 2 &mpc5200_pic 1 1 3[all …]
47 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;123 #clock-cells = <0>;130 #clock-cells = <0>;152 #size-cells = <0>;163 simple-audio-card,dai-link@0 {174 sound-dai = <&codec 0>;196 polling-delay-passive = <0>;197 polling-delay = <0>;[all …]
31 reg = <0 0x80000000 0 0>;40 reg = <0x0 0x86000000 0x0 0x300000>;46 reg = <0x0 0x86300000 0x0 0x100000>;54 reg = <0x0 0x86400000 0x0 0x100000>;59 reg = <0x0 0x86500000 0x0 0x180000>;64 reg = <0x0 0x86680000 0x0 0x80000>;70 reg = <0x0 0x86700000 0x0 0xe0000>;77 reg = <0x0 0x867e0000 0x0 0x20000>;82 reg = <0x0 0x86800000 0x0 0x2b00000>;87 reg = <0x0 0x89300000 0x0 0x600000>;[all …]
