Searched +full:0 +full:x01c40000 (Results 1 – 11 of 11) sorted by relevance
73 - pp0 # Pixel Processor X interrupt (X from 0 to 7)74 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)158 reg = <0x01c40000 0x10000>;
38 #define DAVINCI_PLL1_BASE 0x01c4080039 #define DAVINCI_PLL2_BASE 0x01c40c0040 #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c4100042 #define DAVINCI_SYSTEM_MODULE_BASE 0x01c4000043 #define SYSMOD_VDAC_CONFIG 0x2c44 #define SYSMOD_VIDCLKCTL 0x3845 #define SYSMOD_VPSS_CLKCTL 0x4446 #define SYSMOD_VDD3P3VPWDN 0x4847 #define SYSMOD_VSCLKDIS 0x6c48 #define SYSMOD_PUPDCTL1 0x7c[all …]
30 #define DA8XX_TPCC_BASE 0x01c0000031 #define DA8XX_TPTC0_BASE 0x01c0800032 #define DA8XX_TPTC1_BASE 0x01c0840033 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */34 #define DA8XX_I2C0_BASE 0x01c2200035 #define DA8XX_RTC_BASE 0x01c2300036 #define DA8XX_PRUSS_MEM_BASE 0x01c3000037 #define DA8XX_MMCSD0_BASE 0x01c4000038 #define DA8XX_SPI0_BASE 0x01c4100039 #define DA830_SPI1_BASE 0x01e12000[all …]
72 #size-cells = <0>;74 cpu0: cpu@0 {77 reg = <0>;155 reg = <0x01400000 0x20000>;168 reg = <0x01c00000 0x1000>;175 reg = <0x01d00000 0x80000>;178 ranges = <0 0x01d00000 0x80000>;180 ve_sram: sram-section@0 {183 reg = <0x000000 0x80000>;190 reg = <0x01c0e000 0x1000>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
90 #size-cells = <0>;92 cpu0: cpu@0 {95 reg = <0>;111 #clock-cells = <0>;119 #clock-cells = <0>;135 reg = <0x01c00000 0x30>;142 reg = <0x01d00000 0x80000>;145 ranges = <0 0x01d00000 0x80000>;147 ve_sram: sram-section@0 {150 reg = <0x000000 0x80000>;[all …]
63 #clock-cells = <0>;71 #clock-cells = <0>;81 #size-cells = <0>;83 cpu0: cpu@0 {86 reg = <0>;117 polling-delay-passive = <0>;118 polling-delay = <0>;119 thermal-sensors = <&ths 0>;124 polling-delay-passive = <0>;125 polling-delay = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;183 size = <0x6000000>;184 alloc-ranges = <0x40000000 0x10000000>;210 #clock-cells = <0>;217 #clock-cells = <0>;233 #clock-cells = <0>;240 #clock-cells = <0>;247 #clock-cells = <0>;[all …]
22 #clock-cells = <0>;29 #clock-cells = <0>;37 #size-cells = <0>;39 CPU0: cpu@0 {42 reg = <0x0 0x0>;54 reg = <0x0 0x1>;63 reg = <0x0 0x2>;72 reg = <0x0 0x3>;81 reg = <0x0 0x100>;93 reg = <0x0 0x101>;[all …]
46 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;106 #clock-cells = <0>;113 #clock-cells = <0>;135 #size-cells = <0>;146 simple-audio-card,dai-link@0 {157 sound-dai = <&codec 0>;179 polling-delay-passive = <0>;180 polling-delay = <0>;[all …]
