Searched +full:0 +full:x01c20000 (Results 1 – 15 of 15) sorted by relevance
17 const: 046 #clock-cells = <0>;48 reg = <0x01c20000 0x4>;55 #clock-cells = <0>;57 reg = <0x01c20000 0x4>;64 #clock-cells = <0>;66 reg = <0x01c20000 0x4>;
130 reg = <0x01c20000 0x400>;140 reg = <0x01f01400 0x100>;
14 #clock-cells = <0>;21 #clock-cells = <0>;44 reg = <0x01c00000 0x30>;51 reg = <0x00010000 0x1000>;54 ranges = <0 0x00010000 0x1000>;56 otg_sram: sram-section@0 {59 reg = <0x0000 0x1000>;67 reg = <0x01c20000 0x400>;76 reg = <0x01c20400 0x400>;83 reg = <0x01c20800 0x400>;[all …]
70 #size-cells = <0>;72 cpu@0 {75 reg = <0>;100 #clock-cells = <0>;108 #clock-cells = <0>;124 reg = <0x01000000 0x10000>;136 reg = <0x01100000 0x100000>;137 clocks = <&display_clocks 0>,141 resets = <&display_clocks 0>;145 #size-cells = <0>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
90 #size-cells = <0>;92 cpu0: cpu@0 {95 reg = <0>;111 #clock-cells = <0>;119 #clock-cells = <0>;135 reg = <0x01c00000 0x30>;142 reg = <0x01d00000 0x80000>;145 ranges = <0 0x01d00000 0x80000>;147 ve_sram: sram-section@0 {150 reg = <0x000000 0x80000>;[all …]
86 #clock-cells = <0>;94 #clock-cells = <0>;117 reg = <0x01000000 0x10000>;128 compatible = "allwinner,sun8i-h3-de2-mixer-0";129 reg = <0x01100000 0x100000>;138 #size-cells = <0>;152 reg = <0x01c02000 0x1000>;162 reg = <0x01c0c000 0x1000>;171 #size-cells = <0>;173 tcon0_in: port@0 {[all …]
63 #clock-cells = <0>;71 #clock-cells = <0>;81 #size-cells = <0>;83 cpu0: cpu@0 {86 reg = <0>;117 polling-delay-passive = <0>;118 polling-delay = <0>;119 thermal-sensors = <&ths 0>;124 polling-delay-passive = <0>;125 polling-delay = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
62 #size-cells = <0>;64 cpu0: cpu@0 {71 reg = <0>;115 reg = <0x100>;126 reg = <0x101>;137 reg = <0x102>;148 reg = <0x103>;168 #clock-cells = <0>;181 #clock-cells = <0>;188 #clock-cells = <0>;[all …]
100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;216 #clock-cells = <0>;224 #clock-cells = <0>;241 #clock-cells = <0>;248 #clock-cells = <0>;255 #clock-cells = <0>;257 reg = <0x01c200d0 0x4>;277 reg = <0x01c02000 0x1000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;183 size = <0x6000000>;184 alloc-ranges = <0x40000000 0x10000000>;210 #clock-cells = <0>;217 #clock-cells = <0>;233 #clock-cells = <0>;240 #clock-cells = <0>;247 #clock-cells = <0>;[all …]
52 #define DA8XX_CP_INTC_BASE 0xfffee00056 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)58 #define DA8XX_JTAG_ID_REG 0x1859 #define DA8XX_HOST1CFG_REG 0x4460 #define DA8XX_CHIPSIG_REG 0x17461 #define DA8XX_CFGCHIP0_REG 0x17c62 #define DA8XX_CFGCHIP1_REG 0x18063 #define DA8XX_CFGCHIP2_REG 0x18464 #define DA8XX_CFGCHIP3_REG 0x18865 #define DA8XX_CFGCHIP4_REG 0x18c[all …]
46 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;106 #clock-cells = <0>;113 #clock-cells = <0>;174 polling-delay-passive = <0>;175 polling-delay = <0>;176 thermal-sensors = <&ths 0>;221 polling-delay-passive = <0>;222 polling-delay = <0>;[all …]
138 0x80000000 | 0xf0000000 | UART0139 0x80004000 | 0xf0004000 | UART1140 0x80008000 | 0xf0008000 | UART2141 0x8000c000 | 0xf000c000 | UART3142 0x80010000 | 0xf0010000 | UART4143 0x80014000 | 0xf0014000 | UART5144 0x80018000 | 0xf0018000 | UART6145 0x8001c000 | 0xf001c000 | UART7146 0x80020000 | 0xf0020000 | UART8147 0x80024000 | 0xf0024000 | UART9[all …]
